ARM Cortex-A15 MPCore Processor Technical Reference Manual

Memory Management Unit5.7 External abortsExternal memory errors are defined as those that occur in the memory system rather than thosethat are detected by the MMU. External memory errors are extremely rare. External errors arecaused by errors flagged by the AXI interfaces or generated because of an uncorrected ECCerror in the L1 data cache or L2 cache arrays when the request is external to the Cortex-A15MPCore processor. You can configure external aborts to trap to the monitor mode by setting theEA bit in the Secure Configuration Register to 1. See Secure Configuration Register onpage 4-63 for more information.This section describes external aborts in:• External aborts on data read or write.• Synchronous and asynchronous aborts.See Asynchronous errors on page 7-11 for more information on external memory errors.5.7.1 External aborts on data read or writeExternally generated errors during a data read or write can be asynchronous. This means thatthe r14_abt entry into the abort handler on such an abort might not hold the address of theinstruction that caused the abort.The DFAR is UNPREDICTABLE when an asynchronous abort occurs.For a load multiple or store multiple operation, the address captured in the DFAR is that of theaddress that generated the synchronous external abort.5.7.2 Synchronous and asynchronous abortsTo determine a fault type, read the DFSR for a Data Abort or the IFSR for a Prefetch Abort.The processor supports an Auxiliary Data Fault Status Register for software compatibility. Thisregister provides additional information about the faults generated on data accesses because ofan uncorrected ECC errors. See Auxiliary Data Fault Status Register on page 4-81 for moreinformation. The processor defines an Auxiliary Instruction Fault Status register, but thisregister is not updated.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 5-10ID062913Non-Confidential