ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 2 Memory System7.2.2 Strictly-enforced inclusion property with L1 data cachesThe L2 memory system requires support for inclusion between the L1 data caches and the L2cache. A line that resides in any of the L1 data caches must also reside in the L2 cache. Thisapproach has the following benefits:• Any AXI ReadClean operation that results in a line being in shared state in the L1 datacaches can be returned from the L2 cache. This yields the highest performance fordelivering data to a core.• When powering down the processor, the time to clean and invalidate the entire L1 datacache is more efficient.7.2.3 Enabling and disabling the L2 cacheFor processor requests, the L2 cache is enabled when the C bit of the SCTLR register is enabled,see System Control Register on page 4-54. The cache attributes are provided with each request,taking into account the page attributes that the MMU page tables provided and overriding theseattributes if the corresponding cache enable bit in the SCTLR is disabled.To enable the L2 cache to cache both instructions and data following the reset sequence, youmust:1. Complete the processor reset sequence.2. Program the I bit and C bit of the SCTLR.NoteIf the L2 memory system is configured to support ECC, you must enable this feature byprogramming bit[21] of the L2 Control Register before you can program the C bit. See L2Control Register on page 4-85.To disable the L2 cache, you must use the following sequence:1. Disable the C bit.2. Clean and invalidate the L1 and L2 caches.For ACP requests, the L2 cache is enabled if the request uses Normal Write-Back memoryattributes. The processor searches the L2 cache to determine if the request is valid beforeallocating the line for Normal Write-Back Read-Write Allocate memory.7.2.4 Error Correction CodeThe L2 cache can be configured to support ECC. Some memories within the L2 memory systemsupport ECC when configured. For core instruction and data accesses resulting in an L2 cachehit, where a single-bit error is detected on the data array, the L2 memory system supports in-lineECC correction. Uncorrected data is forwarded to the requesting unit, and in parallel, the ECCcircuitry checks for accuracy. If a single-bit error is detected, any uncorrected data returnedwithin two cycles before the error indicator must be discarded. The L2 memory system beginsto stream corrected data to the requestor.After it is determined that no data is being transferred, the L2 memory system shifts back toreturn uncorrected data until the next single-bit error is detected.For all other single-bit ECC errors detected, the request is flushed from the L2 pipeline and isforced to reissue. The tag bank where the single-bit error occurred, performs aread-modify-write sequence to correct the single-bit error in the array. The request is thenreissued.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 7-4ID062913Non-Confidential