ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control• Only accessible from PL1 or higher.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-2 on page 4-4.Figure 4-4 shows the MPIDR bit assignments.31 30 29 25 24 23 12 11 8 7 2 1 01U ReservedReserved Cluster ID ReservedMTCPU IDFigure 4-4 MPIDR bit assignmentsTable 4-32 shows the MPIDR bit assignments.Table 4-32 MPIDR bit assignmentsBits Name Function[31] - RAO. Indicates that the processor implements the Multiprocessing Extensions register format.[30] U Indicates a Uniprocessor system, as distinct from processor 0 in a multiprocessor system:0 Processor is part of a multiprocessor system.[29:25] - Reserved, RAZ.[24] MT Indicates whether the lowest level of affinity consists of logical processors that are implementedusing a hardware multi-threading type approach:0 Performance of processors at the lowest affinity level is largely independent.[23:12] - Reserved, RAZ.[11:8] Cluster ID Indicates the value read in the CLUSTERID configuration pin. It identifies each processor in amultiprocessor configuration.[7:2] - Reserved, RAZ.[1:0] CPU ID Indicates the processor number in a Cortex-A15 MPCore device. For:• One processor, the CPU ID is 0x0.• Two processors, the CPU IDs are 0x0 and 0x1.• Three processors, the CPU IDs are 0x0, 0x1, and 0x2.• Four processors, the CPU IDs are 0x0, 0x1, 0x2, and 0x3.To access the MPIDR, read the CP15 registers with:MRC p15, 0, , c0, c0, 5; Read Multiprocessor Affinity Register4.3.6 Revision ID RegisterThe REVIDR characteristics are:PurposeProvides implementation-specific minor revision information that canonly be interpreted in conjunction with the MIDR.Usage constraints The REVIDR is:• A read-only register.• Common to the Secure and Non-secure states.• Only accessible from PL1 or higher.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-30ID062913Non-Confidential