ARM Cortex-A15 MPCore Processor Technical Reference Manual

DebugConfigurationsAttributesThe processor implements 6 BRPs, and is specified by theDBGDIDR.BRPs field, see Debug ID Register on page 10-10.See the register summary in Table 10-1 on page 10-6. The debug logicreset value of a DBGBVR is UNK.Figure 10-6 shows the DBGBVR bit assignments.When used for address comparison the DBGBVR bit assignments are:31 2 1 0Instruction address[31:2]00When used for context ID comparison the DBGBVR bit assignments are:31 0Context ID[31:0]Bits Name FunctionFigure 10-6 DBGBVR bit assignmentsTable 10-6 shows the DBGBVR bit assignments when the register is used for addresscomparison.Table 10-6 DBGBVR bit assignments when register is used for address comparison[31:2] Instruction address[31:2] This field indicates bits[31:2] of the virtual address value for comparison[1:0] - This field must be written as b00, otherwise the generation of breakpoint debug events by thisbreakpoint is UNPREDICTABLETable 10-7 shows the DBGBVR bit assignments when the register is used for Context IDcomparison.Table 10-7 Breakpoint Value Register bit assignments when register is used for Context ID comparisonBits Name Function[31:0] Context ID[31:0] This field indicates bits[31:0] of the Context ID value for comparison10.4.6 Breakpoint Control RegistersThe DBGBCR characteristics are:PurposeHolds control information for a breakpoint.Usage constraints Used in conjunction with a DBGBVR, see Breakpoint Value Registers onpage 10-14. Each DBGBVR is associated with a DBGBCR to form aBreakpoint Register Pair (BRP). DBGBVRn is associated withDBGBCRn to form breakpoint n.ConfigurationsAttributesThe processor implements 6 BRPs, and is specified by theDBGDIDR.BRPs field, see Debug ID Register on page 10-10.See the register summary in Table 10-1 on page 10-6. The debug logicreset value of a DBGBCR is UNKNOWN.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 10-15ID062913Non-Confidential