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ARM Cortex-A15 MPCore Processor Technical Reference Manual

ARM Cortex-A15 MPCore Processor Technical Reference Manual

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Generic Interrupt Controller8.3 GIC programmers modelThis section describes the programmers model for the <strong>Cortex</strong>-<strong>A15</strong> <strong>MPCore</strong> GIC in:• Distributor register summary.• Distributor register descriptions on page 8-9.• CPU interface register summary on page 8-15.• CPU interface register descriptions on page 8-16.• Virtual interface control register summary on page 8-18.• Virtual interface control register descriptions on page 8-19.• Virtual CPU interface register summary on page 8-20.• Virtual CPU interface register descriptions on page 8-21.8.3.1 Distributor register summaryThe Distributor centralizes all interrupt sources, determines the priority of each interrupt, andfor each CPU interface dispatches the interrupt with the highest priority to the interface forpriority masking and preemption handling.The Distributor provides a programming interface for:• Globally enabling the forwarding of interrupts to the CPU interfaces.• Enabling or disabling each interrupt.• Setting the priority level of each interrupt.• Routing each interrupt to its target processor.• Setting each shared peripheral interrupt to be level-sensitive or edge-triggered.• Setting each interrupt as either Group 0 or Group 1, see the <strong>ARM</strong> Generic InterruptController (GIC) Architecture Specification for information on interrupt grouping• Forwarding an SGI to one or more target processors.• Visibility of the state of each interrupt.• A mechanism for software to set or clear the pending state of a peripheral interrupt.In addition, the Distributor provides:• Visibility of the state of each interrupt.• A mechanism for software to set or clear the pending state of a peripheral interrupt.The Distributor provides the ability to set interrupts as either:• Secure Group 0.• Non-secure Group 1.• Secure Group 1.See the <strong>ARM</strong> Generic Interrupt Controller (GIC) Architecture Specification for information oninterrupt grouping.Table 8-3 on page 8-8 shows the register map for the Distributor. The offsets in this table arerelative to the Distributor block base address as shown in Table 8-1 on page 8-4.<strong>ARM</strong> DDI 0438I Copyright © 2011-2013 <strong>ARM</strong>. All rights reserved. 8-7ID062913Non-Confidential

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