ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 2 Memory System7.8 Accelerator Coherency PortAccelerator Coherency Port (ACP) is implemented as an AXI3 slave interface that supports thefollowing features:• Configurable 64-bit or 128-bit read and write interfaces.• All burst types such as INCR, WRAP, or FIXED.Note• ACP does not support fixed addressing mode to Normal Memory.• The Cortex-A15 MPCore processor does not support a 64-bit ACE with a 128-bit ACP.This section describes ACP in:• ACP L2 memory interface attributes.• Burst support.• ACP user bits.7.8.1 ACP L2 memory interface attributesTable 7-7 shows the ACP L2 memory interface attributes for the Cortex-A15 MPCoreprocessor. The table lists the maximum possible values for the read and write issuingcapabilities.Attribute Value DescriptionTable 7-7 ACP L2 memory interface attributesACP read acceptance capability 8 4 requests buffered and 4 requests actively being processed.ACP write acceptance capability 8 4 requests buffered and 4 requests actively being processed.7.8.2 Burst supportACP supports a maximum burst lengths of 16 over AXI3. The L2 memory system breaks uptransactions on a cache line boundary, creating additional requests to the L2 pipeline, andpossibly the ACE for L2 cache misses. Ordering is maintained for the requests, and theresponses are generated in the appropriate order on the ACP. For reads, data must be returnedin the order of the original burst received. For writes to Strongly-ordered memory, the BRESPis generated from the final destination. All other BRESPs are generated on the last write datapacket received on the ACP interface.The Cortex-A15 MPCore processor supports fixed burst type transactions only to Device andStrongly-ordered memory.7.8.3 ACP user bitsBecause ACP transactions can be cached in the L2 cache, and the L2 observes inner memorypage attributes, these must be supplied on the ACP.To pass the outer page attributes, use the ARCACHE[3:0] and AWCACHE[3:0] fields.To pass the inner page attributes, use the ARUSER[5:2] and AWUSER[5:2] fields. To pass theinner shareable attribute, use ARUSER[1] and AWUSER[1]. To pass the outer shareableattribute, use ARUSER[0] and AWUSER[0]. See Appendix A Signal Descriptions for moreinformation.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 7-18ID062913Non-Confidential