ARM Cortex-A15 MPCore Processor Technical Reference Manual

DebugTable 10-22 shows the DBGDEVID1 bit assignments.Table 10-22 DBGDEVID1 bit assignmentsBits Name Function[31:4] - Reserved, UNK.[3:0] PCSROffset This field defines the offset applied to DBGPCSR samples:b0000 DBGPCSR samples are offset by a value that depends on the instruction set state.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition for moreinformation.10.4.21 Debug Device ID RegisterThe DBGDEVID characteristics are:PurposeExtends the DBGDIDR by describing other features of the debugimplementation.Usage constraints Use in conjunction with DBGDIDR to find the features of the debugimplementation. See DBGDIDR bit assignments on page 10-10.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 10-1 on page 10-6.Figure 10-24 shows the DBGDEVID bit assignments.31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0CIDMaskAuxRegs DoubleLock VirtExtnsPCsampleWPAddrMaskBPAddrMaskVectorCatchFigure 10-24 DBGDEVID bit assignmentsTable 10-23 shows the DBGDEVID bit assignments.Table 10-23 DBGDEVID bit assignmentsBits Name Function[31:28] CIDMask CIDMask. This field indicates the level of support for the Context ID matching breakpointmasking capability.b0000 Context ID masking not implemented.[27:24] AuxRegs Specifies support for the Debug External Auxiliary Control Register. See Debug ExternalAuxiliary Control Register on page 10-13:b0001 The processor supports Debug External Auxiliary Control Register.[23:20] DoubleLock Specifies support for the OS Double Lock Register:b0001 The processor supports OS Double Lock Register.[19:16] VirExtns Specifies the implementation of the Virtualization Extensions to the Debug architecture:b0001 The processor implements the Virtualization Extensions to the Debugarchitecture.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 10-31ID062913Non-Confidential