ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-55 SCR bit assignments (continued)Bits Name Function[5] AW A bit writable. This bit controls whether CPSR.A can be modified in Non-secure state. For theCortex-A15 MPCore processor:• This bit has no effect on whether CPSR.A can be modified in Non-secure state. The AW bitcan be modified in either security state.• This bit, with the HCR.AMO bit, determines whether CPSR.A has any effect on exceptionsthat are routed to a Non-secure mode.[4] FW F bit writable. This bit controls whether CPSR.F can be modified in Non-secure state. For theCortex-A15 MPCore processor:• This bit has no effect on whether CPSR.F can be modified in Non-secure state. The FW bitcan be modified in either security state.• This bit, with the HCR.FMO bit, determines whether CPSR.F has any effect on exceptionsthat are routed to a Non-secure mode.[3] EA External Abort handler. This bit controls which mode takes external aborts:0 External aborts taken in Abort mode. This is the reset value.1 External aborts taken in Monitor mode.[2] FIQ FIQ handler. This bit controls which mode takes FIQ exceptions:0 FIQs taken in FIQ mode. This is the reset value.1 FIQs taken in Monitor mode.[1] IRQ IRQ handler. This bit controls which mode takes IRQ exceptions:0 IRQs taken in IRQ mode. This is the reset value.1 IRQs taken in Monitor mode.[0] NS Non Secure bit. Except when the processor is in Monitor mode, this bit determines the securitystate of the processor:0 Secure. This is the reset value.1 Non-secure.NoteWhen the processor is in Monitor mode, it is always in Secure state, regardless of the value of theNS bit. The value of the NS bit also affects the accessibility of the Banked CP15 registers inMonitor mode.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition for moreinformation on the NS bit.To access the SCR, read or write the CP15 register with:MRC p15, 0, , c1, c1, 0; Read Secure Configuration Register dataMCR p15, 0, , c1, c1, 0; Write Secure Configuration Register data4.3.31 Non-Secure Access Control RegisterThe NSACR characteristics are:PurposeDefines the Non-secure access permission to coprocessors CP10 andCP11, and to the following bits:• The SMP bit of the ACTLR, see Auxiliary Control Register onpage 4-57.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-65ID062913Non-Confidential