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ARM Cortex-A15 MPCore Processor Technical Reference Manual

ARM Cortex-A15 MPCore Processor Technical Reference Manual

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Program Trace Macrocell12.7.19 Integration Mode Control RegisterThe ETMITCTRL Register enables topology detection and integration testing.When bit[0] is set to 1, the PTM enters an integration mode. On reset this bit is cleared to 0.Before entering integration mode, the PTM must be powered up and in programming mode.This means bit[0] of the Main Control Register is set to 0, and bit[10] of the Main ControlRegister is set to 1. See Main Control Register on page 12-14.After leaving integration mode, the PTM must be reset before attempting to perform tracing.The CoreSight Program Trace Flow Architecture Specification describes the operation of thisregister in the PTM.12.7.20 Peripheral Identification RegistersThe Peripheral Identification Registers provide standard information required for all CoreSightcomponents. They are a set of eight registers, listed in register number order in Table 12-22.Table 12-22 Summary of the Peripheral ID RegistersRegister Value OffsetPeripheral ID4 0x04 0xFD0Peripheral ID5 0x00 0xFD4Peripheral ID6 0x00 0xFD8Peripheral ID7 0x00 0xFDCPeripheral ID0 0x5F 0xFE0Peripheral ID1 0xB9 0xFE4Peripheral ID2 0x3B 0xFE8Peripheral ID3 0x00 0xFECOnly bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, theeight Peripheral ID Registers define a single 64-bit Peripheral ID.The CoreSight Program Trace Flow Architecture Specification describes these registers.12.7.21 Component Identification RegistersThere are four read-only Component Identification Registers, Component ID0 to ComponentID3. Table 12-23 shows these registers.Table 12-23 Summary of the Component Identification RegistersRegister Value OffsetComponent ID0 0x0D 0xFF0Component ID1 0x90 0xFF4Component ID2 0x05 0xFF8Component ID3 0xB1 0xFFC<strong>ARM</strong> DDI 0438I Copyright © 2011-2013 <strong>ARM</strong>. All rights reserved. 12-30ID062913Non-Confidential

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