ARM Cortex-A15 MPCore Processor Technical Reference Manual

Functional DescriptionPowerup resetThe full powerup reset initializes all logic in the Cortex-A15 MPCore processor. You must applypowerup reset to the Cortex-A15 MPCore processor when power is first applied to the SoC.Logic in all clock domains are placed in a benign state following the deassertion of the resetsequence.Figure 2-7 shows the full powerup reset sequence for the Cortex-A15 MPCore processor.CLKnCPUPORESET[3:0]nCORERESET[3:0]optionalnCXRESET[3:0]optionalnDBGRESET[3:0]optionalnL2RESETnPRESETDBG16 CLK cycles minimum16 CLK cycles minimum16 CLK cycles minimum16 CLK cycles minimum16 CLK cycles minimum16 PCLKDBG cycles minimumFigure 2-7 Powerup reset timingOn full powerup reset for the Cortex-A15 MPCore processor, perform the following resetsequence:1. Apply nCPUPORESET, nL2RESET, and nPRESETDBG. The remaining processorresets, nCORERESET, nCXRESET, and nDBGRESET can be asserted, but is notrequired.2. nCPUPORESET and nL2RESET must be asserted for at least 16 CLK cycles.nPRESETDBG must be asserted for at least16 PCLKDBG cycles. Holding the resets forthis duration ensures that the resets have propagated to all locations within the processor.3. nL2RESET must be deasserted in the same cycle as the processor resets, or before anyof the processor resets are deasserted.Individual processor powerup reset initializes all logic in a single processor. You must apply thepowerup reset when the individual processor is in powered state. In implementations where eachprocessor has its own power supply, the powerup reset holds the processor in a reset state so thatpower to the processor can be safely applied. You must apply the correct sequence beforeapplying a powerup reset to that processor.For individual processor powerup reset:• nCPUPORESET for that processor must be asserted for at least 16 CLK cycles.• nL2RESET must not be asserted while any individual processor is active.• nPRESETDBG must not be asserted while any individual processor is actively beingdebugged in normal operating mode or during external debug over power down.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 2-16ID062913Non-Confidential