ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control4.3.39 Hyp Translation Control RegisterThe processor does not use any implementation-defined bits in the HTCR, so these bits areUNK/SBZP.4.3.40 Data Fault Status RegisterThe DFSR characteristics are:PurposeHolds status information about the last data fault.Usage constraints The DFSR is:• A read/write register.• Banked for Secure and Non-secure states.• Only accessible from PL1 or higher.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-6 on page 4-6.There are two formats for this register. The current translation table format determines whichformat of the register is used. This section describes:• DFSR format when using the Short-descriptor translation table format.• DFSR format when using the Long-descriptor translation table format on page 4-77.DFSR format when using the Short-descriptor translation table formatFigure 4-31 shows the DFSR bit assignments when using the Short-descriptor translation tableformat.31 14 13 12 11 10 9 8 7 4 3 0Reserved 0DomainFS[3:0]ReservedFS[4]WnRExTCMFigure 4-31 DFSR bit assignments for Short-descriptor translation table formatARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-75ID062913Non-Confidential