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ARM Cortex-A15 MPCore Processor Technical Reference Manual

ARM Cortex-A15 MPCore Processor Technical Reference Manual

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System Control4.3.2 Cache Type RegisterThe CTR characteristics are:PurposeProvides information about the architecture of the caches.Usage constraints The CTR is:• A read-only register.• Common to the Secure and Non-secure states.• Only accessible from PL1 or higher.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-2 on page 4-4.Figure 4-2 shows the CTR bit assignments.31 29 28 27 24 23 20 19 16 15 14 13 4 3 010 0 0 CWG ERG DminLine L1ip 0 0 0 0 0 0 0 0 0 0IminLineFormatFigure 4-2 CTR bit assignmentsTable 4-30 shows the CTR bit assignments.Table 4-30 CTR bit assignmentsBits Name Function[31:29] Format Indicates the implemented CTR format:b100 <strong>ARM</strong>v7 format.[28] - Reserved, RAZ.[27:24] CWG Cache Writeback Granule. Log 2 of the number of words of the maximum size of memory that canbe overwritten as a result of the eviction of a cache entry that has had a memory location in itmodified:0x4Cache writeback granule size is 16 words.[23:20] ERG Exclusives Reservation Granule. Log 2 of the number of words of the maximum size of thereservation granule that has been implemented for the Load-Exclusive and Store-Exclusiveinstructions:0x4Exclusive reservation granule size is 16 words.[19:16] DminLine Log 2 of the number of words in the smallest cache line of all the data and unified caches that theprocessor controls:0x4Smallest data cache line size is 16 words.[15:14] L1ip Level 1 instruction cache policy. Indicates the indexing and tagging policy for the L1 instructioncache:b11Physical index, physical tag.[13:4] - Reserved, RAZ.[3:0] IminLine Log 2 of the number of words in the smallest cache line of all the instruction caches that theprocessor controls. The primary input IMINLN defines the reset value:0x3Smallest instruction cache line size is 8 words, the IMINLN signal is LOW.0x4Smallest instruction cache line size is 16 words, the IMINLN signal is HIGH.<strong>ARM</strong> DDI 0438I Copyright © 2011-2013 <strong>ARM</strong>. All rights reserved. 4-28ID062913Non-Confidential

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