ARM Cortex-A15 MPCore Processor Technical Reference Manual

RevisionsTable B-2 Differences between issue A and issue B (continued)Change Location AffectsAdded bit[10] Disable Non-secure debug array read to the L2Auxiliary Control RegisterUpdated description of Non-cacheable streamingenhancementL2 Auxiliary Control Register on page 4-100Non-cacheable streaming enhancement on page 6-9r0p0r0p0Updated ID number of Software Generated Interrupt (SGI) Interrupt sources on page 8-4 r0p0Added event number 0x62 and 0x63 to the PMU event table Table 11-7 on page 11-15 r1p0Updated description for bits[3:0] of the ETMIDR ETM ID Register on page 12-20 r1p0Updated the value for Peripheral ID2 Register • Table 10-24 on page 10-32• Table 11-5 on page 11-12• Table 12-22 on page 12-30.r1p0Updated trigger input name of PMU generated interrupt Table 13-1 on page 13-3 r0p0Clarified the step instructions for using the Advanced SIMDand VFP in Secure stateClarified the step instructions for using the Advanced SIMDand VFP in Secure state and Non-secure stateClarified the step instructions for using the Advanced SIMDand VFP in Hyp modeUsing the Advanced SIMD and VFP in Secure state onlyon page 14-5Using the Advanced SIMD and VFP in Secure state andNon-secure state other than Hyp mode on page 14-5Using the Advanced SIMD and VFP in Hyp mode onpage 14-5r0p0r0p0r0p0Clarified description of the GIC signals Table A-4 on page A-6 r0p0Clarified description of the EVENTI and EVENTO signals Table A-6 on page A-9 r0p0Updated and moved SYNCREQx from Miscellaneous PTMinterface signals table to ATB interface signals tableTable A-28 on page A-23r0p0Table B-3 Differences between issue B and issue CChange Location AffectsUpdated description for L2 wait for interrupt L2 Wait for Interrupt on page 2-23 r2p0Updated the reset value of the Main ID Register • Table 4-2 on page 4-4• Table 4-16 on page 4-14Corrected the reset value of the ID_PFR0 Register • Table 4-2 on page 4-4• Table 4-16 on page 4-14r2p0All revisionsUpdated bits[23:20] of the Main ID Register Main ID Register on page 4-27 r2p0Clarified description of bits[11:8] of the ID_PFR0 Register Processor Feature Register 0 on page 4-31 All revisionsUpdated L2ACTLR bit[5] of the L2 Auxiliary ControlRegisterL2 Auxiliary Control Register onpage 4-100r2p0Updated description of GIC memory-map GIC memory-map on page 8-3 r2p0Updated the value for Peripheral ID2 Register • Table 10-24 on page 10-32• Table 11-5 on page 11-12• Table 12-22 on page 12-30r2p0ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. B-2ID062913Non-Confidential