ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 1 Memory SystemExternal global monitorIf synchronization primitives are used for memory pages that are Strongly-ordered, Device, orInner-Shareable Normal Non-Cacheable, a global monitor must be provided in the interconnect.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition for moreinformation. The memory requests are sent on the AXI interface as Read-Exclusive orWrite-Exclusive. See the AMBA AXI and ACE Protocol Specification for more information.Note• Use of synchronization primitives on addresses in regions marked as Strongly-ordered orDevice is UNPREDICTABLE in the ARMv7-A Architecture. Code that makes such accessesis not portable.• Load-Exclusive and Store-Exclusive requests are not supported to shareable NormalWrite-Through memory.• Load-Exclusive and Store-Exclusive requests are not supported to shareable NormalWrite-Back memory if the cache is disabled, SCTLR.C is 0.6.4.6 LDRT and STRT instructionsThe LDRT, LDRHT, LDRBT, STRT, STRHT, and STRBT instructions are used in privileged modes toemulate user mode instructions and to enforce user mode permissions. These instructions are forall memory types when enforcing permission checking against the permissions that the pagetable specifies. The User mode permissions from the page table are used instead of theprivileged mode permissions.These instructions are also used to modify the privileged and user information on the ARPROTand AWPROT signals on the AXI. This is required if external permission checking hardwareexists in the fabric memory.The LDRT and STRT instructions for Strongly-ordered and Device pages appear on the AXI withan AxPROT value that indicates user mode access. However, the same instructions for NormalMemory might not always result in AXI transactions with an AxPROT value that indicates usermode access. This is because any Normal Memory page permits speculative prefetching at anytime. Those prefetch requests, either caused by hardware prefetching or speculative prefetchingtriggered by flushed memory instructions, can have a value of the AxPROT field that indicatesprivileged mode access. This reflects the mode of the processor during the prefetch.For Normal Write-Through Cacheable or Non-Cacheable memory, the processor can still accessthe memory speculatively, and can merge multiple stores together before issuing them to theAXI. Because of this, you must use the LDRT and STRT instructions to present user mode onAxPROT if the LDRT and STRT instructions are preceded and followed by DMB instructions:• DMB.• LDRT or STRT.• DMB.The DMB instructions prevent the LDRT or STRT instruction from hitting any previously requestedread data, or from merging with any other requests. The DMB instructions can be DMBSY, DMBISH,DMBISH, and DMBOSH.6.4.7 Preload instruction behaviorThe Cortex-A15 MPCore processor supports both the PLD and PLDW prefetch hint instructions.For Normal Write-Back Cacheable memory page, the preload instructions cause the line to beallocated to the L1 data cache of the executing core. The PLD instruction brings the line into theARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 6-10ID062913Non-Confidential