ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-52 shows the SCTLR bit assignments.Table 4-52 SCTLR bit assignmentsBits Name Access Function[31] - - Reserved, UNK/SBZP.[30] TE Banked Thumb Exception enable. This bit controls whether exceptions are taken in ARM or Thumb state:0 Exceptions, including reset, taken in ARM state.1 Exceptions, including reset, taken in Thumb state.The primary input CFGTE defines the reset value of the TE bit.[29] AFE Banked Access flag enable. This bit enables use of the AP[0] bit in the translation table descriptors as theAccess flag. It also restricts access permissions in the translation table descriptors to the simplifiedmodel as described in the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition:0 In the translation table descriptors, AP[0] is an access permissions bit. The fullrange of access permissions is supported. No Access flag is implemented. This isthe reset value.1 In the translation table descriptors, AP[0] is the Access flag. Only the simplifiedmodel for access permissions is supported.When TTBCR.EAE is set to 1, to enable use of the Long-descriptor translation table format, thisbit is UNK/SBOP.[28] TRE Banked TEX remap enable. This bit enables remapping of the TEX[2:1] bits for use as two translationtable bits that can be managed by the operating system. Enabling this remapping also changes thescheme used to describe the memory region attributes in the VMSA:0 TEX remap disabled. TEX[2:0] are used, with the C and B bits, to describe thememory region attributes. This is the reset value.1 TEX remap enabled. TEX[2:1] are reassigned for use as bits managed by theoperating system. The TEX[0], C and B bits are used to describe the memoryregion attributes, with the MMU remap registers.When TTBCR.EAE is set to 1, to enable use of the Long-descriptor translation table format, thisbit is UNK/SBOP.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition for moreinformation.[27] - - Reserved, RAZ/WI.[26] - - Reserved, RAZ/SBZP.[25] EE Banked Exception Endianness. The value of this bit defines the value of the CPSR.E bit on entry to anexception vector, including reset. This value also indicates the endianness of the translation tabledata for translation table lookups:0 Little endian.1 Big endian.The primary input CFGEND defines the reset value of the EE bit.[24] - - Reserved, RAZ/WI.[23:22] - - Reserved, RAO/SBOP.[21] - - Reserved, RAZ/WI.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-55ID062913Non-Confidential