ARM Cortex-A15 MPCore Processor Technical Reference Manual

DebugFigure 10-7 shows the DBGBCR bit assignments.31 29 28 24 23 20 19 16 15 14 13 12 9 8 5 4 3 2 1 0MASKBTLBNSSCReservedBASPMC EReservedHMCReservedFigure 10-7 DBGBCR bit assignmentsTable 10-8 shows the DBGBCR bit assignments.Table 10-8 DBGBCR bit assignmentsBits Name Function[31:29] - Reserved.[28:24] MASK Address range mask. The processor does not support address range masking.[23:20] BT Breakpoint Type. This field controls the behavior of debug event generation. This includes themeaning of the value held in the associated DBGBVR, indicating whether it is an instructionaddress match or mismatch or a Context match. It also controls whether the breakpoint is linkedto another breakpoint.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition for the breakpointtype values and meanings.[19:16] LBN Linked Breakpoint Number. If this breakpoint is programmed for Linked instruction addressmatch or mismatch then this field must be programmed with the number of the breakpoint thatholds the Context match to be used in the combined instruction address and Context comparison.Otherwise, this field must be programmed to b0000.Reading this register returns an UNKNOWN value for this field, and the generation of debug eventsis UNPREDICTABLE, if either:• This breakpoint is not programmed for Linked instruction address match or mismatch andthis field is not programmed to b0000.• This breakpoint is programmed for Linked instruction address match or mismatch and thebreakpoint indicated by this field does not support Context matching or is not programmedfor Linked Context matching.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition for moreinformation.[15:14] SSC Security State Control. This field enables the breakpoint to be conditional on the security state ofthe processor. This field is used with the Hyp Mode Control (HMC), and Privileged Mode Control(PMC), fields. See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition forpossible values of the fields, and the mode and security states that can be tested.This field must be programmed to b00 if DBGBCR.BT is programmed for Linked Context match.If this is not done, the generation of debug events by this breakpoint is UNPREDICTABLE.NoteWhen this field is set to a value other than b00, the SSC field controls the processor security statein which the access matches, not the required security attribute of the access.[13] HMC Hyp Mode Control bit. This field is used with the SSC and PMC fields. See the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition for possible values of the fields, and the modeand security states that can be tested.This field must be programmed to 0 if DBGBCR.BT is programmed for Linked Context match.If this is not done, the generation of debug events by this breakpoint is UNPREDICTABLE.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 10-16ID062913Non-Confidential