ARM Cortex-A15 MPCore Processor Technical Reference Manual

Program Trace MacrocellBits[2:0] of this register are not implemented and read as zero. In all other respects, theCoreSight Program Trace Flow Architecture Specification describes the operation of thisregister in the PTM.12.7.7 ETM ID RegisterThe ETMIDR characteristics are:Purpose • Holds the PTM architecture variant.• Defines the programmers model for the PTM.Usage constraints There are no usage constraints.ConfigurationsAvailable in all PTM configurations.Attributes See the register summary in Table 12-4 on page 12-11.Figure 12-7 shows the ETMIDR bit assignments.31 24 23 21 20 19 18 17 16 15 12 11 8 7 4 3 00 1 0 0 0 0 0 1 1 1 11 1 1 10 0 1 1 0 0 0 10 0 1 0Implementer codeReservedReservedMajorMinorRAOSecurity Extensions supported32-bit Thumb instructions supportedReservedArchitectureversion numberImplementationrevisionFigure 12-7 ETMIDR bit assignmentsTable 12-10 shows the ETMIDR bit assignments.Table 12-10 ID Register bit assignmentsBits Name Function[31:24] Implementer code Indicates the implementer:0x41 ARM.[23:21] - RAZ.[20] - RAO.[19] Security Extensions supported Support for Security Extensions. The value of this bit is 1, indicating that theprocessor implements the ARM architecture Security Extensions.[18] 32-bit Thumb instructions supported Support for 32-bit Thumb instructions. The value of this bit is 1, indicating that a32-bit Thumb instruction is traced as a single instruction.[17:16] - RAZ.[15:12] - This field reads as b1111.[11:8] Major architecture version Indicates the major architecture version number. This field reads as b0011.[7:4] Minor architecture version Indicates the minor architecture version number. This field reads as b0001.[3:0] Implementation revision Indicates the implementation revision. This field reads as b0011.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 12-20ID062913Non-Confidential