ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0SWP_fracPSR_M_instrsSynchPrim_instrs_fracBarrier_instrsSMC_instrsWriteback_instrsWithShifts_instrsUnpriv_instrsTable 4-45 shows the ID_ISAR4 bit assignments.Figure 4-17 ID_ISAR4 bit assignmentsTable 4-45 ID_ISAR4 bit assignmentsBits Name Function[31:28] SWP_frac Indicates support for the memory system locking the bus for SWP or SWPB instructions:0x1Processor supports SWP and SWPB instruction but only in a uniprocessor context.SWP and SWPB do not guarantee whether memory accesses from other masters cancome between the load memory access and the store memory access of the SWPor SWPB instruction.[27:24] PSR_M_instrs Indicates the supported M profile instructions to modify the PSRs:0x0None supported.[23:20] SynchPrim_instrs_frac This field is used with the SynchPrim_instrs_frac field of ID_ISAR3 to indicate the supportedSynchronization Primitive instructions.0x0Processor supports:• LDREX and STREX instructions.• CLREX, LDREXB, LDREXH, STREXB, and STREXH instructions.• LDREXD and STREXD instructions.[19:16] Barrier_instrs Indicates the supported Barrier instructions in the ARM and Thumb instruction sets:0x1Processor supports DMB, DSB, and ISB barrier instructions.[15:12] SMC_instrs Indicates the supported SMC instructions:0x1Processor supports SMC instruction.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-47ID062913Non-Confidential