ARM Cortex-A15 MPCore Processor Technical Reference Manual

Functional DescriptionIf the L1 data cache of a processor that is in WFI low-power state contains data that is likely tobe the target of frequent snoops from other processors, entering quiescent state and retention islikely to be inefficient.When using the processor retention feature, you must consider the following points:• During processor reset, QREQn must be deasserted HIGH while QACCEPTn isasserted LOW.• Each QREQn request is followed by the assertion of either QACCEPTn or QDENY, butnot both. QACCEPTn cannot be asserted LOW at the same time as QDENY is assertedHIGH.• QACTIVE, QACCEPTn and QDENY are synchronous outputs.• QREQn is an asynchronous input.• In a system that does not use the processor retention feature, QREQn must be tied HIGH.• QACTIVE is only a hint. The external power controller can assert QREQn LOW at anytime after reset. If QACTIVE is asserted HIGH, it is likely that the retention request canbe denied.• The Enable CPU WFI retention bit in the L2 Auxiliary Control Register, see L2 AuxiliaryControl Register on page 4-100, must be set to enable this feature. If it is not set, allassertions of QREQn HIGH receive QDENY responses.• If any processor sets the Force NEON/VFP clock enable active or Force main clockenable active bits in the Auxiliary Control Register, see Auxiliary Control Register onpage 4-57, this feature is disabled and all assertions of QREQn receive QDENYresponses.NEON and VFP clock gatingThe Cortex-A15 MPCore processor supports dynamic high-level clock gating of the NEON andVFP unit to reduce dynamic power dissipation.With the NEON and VFP unit powered up, the clock to the unit is enabled when an AdvancedSIMD or VFP instruction is detected in the pipeline, and is disabled otherwise.You can set bit[29] of the Auxiliary Control Register, ACTLR, to 1 to disable dynamic clockgating of the NEON and VFP unit. See Auxiliary Control Register on page 4-57.L2 control and tag banks clock gatingThe Cortex-A15 MPCore processor supports dynamic high-level clock gating of the shared L2control logic and the four L2 tag banks to reduce dynamic power dissipation.The L2 tag bank clocks are only enabled when a corresponding access is detected in the pipeline.The L2 control logic is disabled after 256 consecutive idle cycles. It is then enabled when an L2access is detected, with an additional 4-cycle penalty for the wake up before the access isserviced.You can set bit[28] of the L2 Auxiliary Control Register, L2ACTLR, to 1 to disable dynamicclock gating of the L2 tag banks. See L2 Auxiliary Control Register on page 4-100.You can set bit[27] of the L2 Auxiliary Control Register, L2ACTLR, to 1 to disable dynamicclock gating of the L2 control logic. See L2 Auxiliary Control Register on page 4-100.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 2-27ID062913Non-Confidential