ARM Cortex-A15 MPCore Processor Technical Reference Manual

Memory Management Unit5.3 TLB match processThe Virtualization Extensions and the Security Extensions provide for multiple virtual addressspaces that are translated differently. The TLB entries store all the required context informationto facilitate a match and avoid the requirement for a TLB flush on a context or virtual machineswitch. Each TLB entry contains a virtual address, page size, physical address, and a set ofmemory properties that include the memory type and access permissions. Each entry is markedas being associated with a particular ASID, or as global for all application spaces. The TLBentry also contains a field to store the VMID that brought in the entry, applicable to accessesmade from the Non-secure state, as defined by the Virtualization Extensions. There is also a bitthat records whether that TLB entry is allocated on a Hyp mode request. A TLB entry matchoccurs when the following conditions are met:• Its virtual address, moderated by the page size such as the virtual address bits[31:N],where N is log2 of the page size for that translation stored in the TLB entry, matches thatof the requested address.• The Non-secure TLB ID, NSTID, matches the Secure or Non-secure state of the requests.• The Hyp mode bit matches whether the request was made from Hyp mode.• The ASID matches the current ASID held in the CONTEXTIDR, TTBR0, or TTBR1register or the entry is marked global.• The VMID matches the current VMID held in the VTTBR register.Note• For a request originating from Hyp mode, the ASID and VMID match are ignored.• For a request originating from Secure state, the VMID match is ignored.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 5-4ID062913Non-Confidential