ARM Cortex-A15 MPCore Processor Technical Reference Manual

Generic Interrupt ControllerThe Cortex-A15 MPCore processor implements the GICC_APR0 according to therecommendations described in the ARM Generic Interrupt Controller ArchitectureSpecification.Table 8-10 shows the Cortex-A15 MPCore GICC_APR0 implementation.Table 8-10 Active Priority Register implementationNumber ofgrouppriority bitsPreemptionlevelsMinimum legalvalue of SecureGICC_BPRMinimum legal valueof Non-secureGICC_BPRActive PriorityRegistersimplementedView of Active PriorityRegisters forNon-secure accesses5 32 2 3 GICC_APR0[31:0]GICC_NSAPR0 [31:16]appears as GICC_APR0[15:0]Non-secure Active Priority RegisterThe GICC_NSAPR0 characteristics are:PurposeProvides support for preserving and restoring state in power-managementapplications.Usage constraints. This register is only accessible from a Secure access.ConfigurationsAvailable if the GIC is implemented.Attributes See the register summary in Table 8-9 on page 8-15.The Cortex-A15 MPCore processor implements the GICC_NSAPR0 according to therecommendations described in the ARM ® Generic Interrupt Controller ArchitectureSpecification. It is consistent with the GICC_APR0 Register.CPU Interface Identification RegisterThe GICC_IIDR characteristics are:PurposeProvides information about the implementer and revision of the CPUinterface.Usage constraints. There are no usage constraints.ConfigurationsAvailable if the GIC is implemented.Attributes See the register summary in Table 8-9 on page 8-15.Figure 8-6 shows the GICC_IIDR bit assignments.31 20 19 16 15 12 110ProductIDArchitectureversionRevisionImplementerFigure 8-6 GICC_IIDR bit assignmentsARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 8-17ID062913Non-Confidential