ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-64 IFSR bit assignments for Long-descriptor translation table format (continued)Bits Name Function[9] - RAO.[8:6] - Reserved, UNK/SBZP.[5:0] Status Fault Status bits. This field indicates the type of exception generated. Any encoding not listed isreserved:b0001LL Translation fault, LL bits indicate level.b0010LL Access flag fault, LL bits indicate level.b0011LL Permission fault, LL bits indicate level.b010000 Synchronous external abort.b011000 Synchronous parity error on memory access.b0101LL Synchronous external abort on translation table walk, LL bits indicate level.b0111LL Synchronous parity error on memory access on translation table walk, LL bitsindicate level.b100010 Debug event.Table 4-65 shows how the LL bits in the Status field encode the lookup level associated with theMMU fault.Table 4-65 Encodings of LL bits associated with the MMU faultLL BitsMeaning00 Reserved01 First level10 Second level11 Third levelNoteIf a Data Abort exception is generated by an instruction cache maintenance operation, the faultis reported as a Cache Maintenance fault in the DFSR or HSR with the appropriate Fault Statuscode. For such exceptions reported in the DFSR, the corresponding IFSR is UNKNOWN.To access the IFSR, read or write the CP15 register with:MRC p15, 0, , c5, c0, 1; Read Instruction Fault Status RegisterMCR p15, 0, , c5, c0, 1; Write Instruction Fault Status Register4.3.42 Auxiliary Data Fault Status RegisterThe ADFSR characteristics are:PurposeHolds the information about asynchronous L1 and L2 ECC double-biterrors.Usage constraints The ADFSR is:• A read/write register.• Banked for Secure and Non-secure states.• Accessible from PL1 or higher.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-81ID062913Non-Confidential