ARM Cortex-A15 MPCore Processor Technical Reference Manual

Program Trace Macrocell31 26 25 24 23 4 3 0ReservedReservedExclude/include flagTrace control enableAddress comparators4 3 2 1Figure 12-6 ETMECR1 bit assignmentsTable 12-9 shows the ETMECR1 bit assignments.Table 12-9 ETMECR1 bit assignmentsBits Name Function[31:26] - SBZP.[25] Trace control enable Trace start/stop control enable. The possible values of this bit are:0 Tracing is unaffected by the trace start/stop logic.1 Tracing is controlled by the trace on and off addresses configured for the tracestart/stop logic.The trace start/stop event resource is not affected by the value of this bit. See[24] Exclude/include flag Exclude/include flag. The possible values of this bit are:0 Include. The specified address range comparators indicate the regions wheretracing can occur. No tracing occurs outside this region.1 Exclude. The specified address range comparators indicate regions to be excludedfrom the trace. When outside an exclude region, tracing can occur.[23:4] - SBZP.[3:0] Address comparators When this bit is set to 1, it selects an address range comparator, from 4 to 1, for exclude/includecontrol. For example, bit[0] set to 1 selects address range comparator 1.Tracing all instructionsTo trace all processor execution:• Set bit[24], the exclude/include flag, in the ETMECR1 to 1.• Set all other bits in the ETMECR1 to 0.• Set the ETMTEEVER to 0x0000006F (TRUE).This has the effect of excluding nothing, that is, tracing everything, and setting the trace enableevent to always true, with the start/stop logic ignored.12.7.6 Synchronization Frequency RegisterThe ETMSYNCFR characteristics are:PurposeHolds the trace synchronization frequency value.Usage constraints There are no usage constraints.ConfigurationsAvailable in all PTM configurations.Attributes See the register summary in Table 12-4 on page 12-11.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 12-19ID062913Non-Confidential