ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control31 24 23 22 21 18 17 6 50RAMID = 0x14 Way Physical address [17:6]ReservedReservedThe RAMINDEX address bits for accessing L2 dirty RAM are:Figure 4-57 RAMINDEX bit assignments for L2 dirty RAMWay[3:0]PA[17:8]PA[7:6]Way select.Row select.Tag bank select.The data returned from accessing L2 dirty RAM are:DL1DATA3 32'b0.DL1DATA2 32'b0.DL1DATA1 32'b0.DL1DATA0 Dirty data[17:0].Figure 4-58 shows the RAMINDEX bit assignments for accessing L2 TLB RAM.31 24 23 20 19 18 17 7 60RAMID = 0x18 Reserved Way ReservedTLB entryThe RAMINDEX address bits for accessing L2 TLB RAM are:Figure 4-58 RAMINDEX bit assignments for L2 TLB RAMWayTLB entryWay select.Selects one of the 128 entries in each way.The data returned from accessing L2 TLB RAM are:DL1DATA3 TLB entry data[99:96].DL1DATA2 TLB entry data[95:64].DL1DATA1 TLB entry data[63:32].DL1DATA0 TLB entry data[31:0].For example, to read one entry in the instruction side L1 data array:LDR R0, =0x01000D80;MCR p15, 0, R0, c15, c4, 0; Read I-L1 TLB data into IL1Data0-2DSBISBMRC p15, 0, R1, c15, c0, 0; Move IL1Data0 Register to R1MRC p15, 0, R2, c15, c0, 1; Move IL1Data1 Register to R2MRC p15, 0, R3, c15, c0, 2; Move IL1Data2 Register to R3To access the RAMINDEX, write the CP15 register with:MCR p15, 0, , c15, c4, 0; Write RAM Index RegisterARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-99ID062913Non-Confidential