ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-53 ACTLR bit assignments (continued)Bits Name Function[2] a Limit to one loop buffer detect perflushLimits to one loop buffer detect per flush:0 Normal behavior. This is the reset value.1 Limits to one loop buffer detect per flush.[1] a Disable loop buffer Disables loop buffer:0 Enables loop buffer. This is the reset value.1 Disables loop buffer.[0] a Enable invalidates of BTB Enables invalidate of BTB:0 The CP15 Invalidate Instruction Cache All and InvalidateInstruction Cache by MVA instructions only invalidates theinstruction cache array. This is the reset value.1 The CP15 Invalidate Instruction Cache All and InvalidateInstruction Cache by MVA instructions invalidates theinstruction cache array and branch target buffer.a. This bit is provided for debugging and characterization purpose only. For normal operation, ARM recommends that you do not change thevalue of this bit from its reset value.To access the ACTLR, read or write the CP15 register with:MRC p15, 0, , c1, c0, 1 ; Read Auxiliary Control RegisterMCR p15, 0, , c1, c0, 1 ; Write Auxiliary Control Register4.3.29 Coprocessor Access Control RegisterThe CPACR characteristics are:PurposeControls access to coprocessors CP10 and CP11.Usage constraints The CPACR:• Is a read/write register.• Is Common to the Secure and Non-secure states.• Is only accessible from PL1 or higher.• Has no effect on instructions executed in Hyp mode.ConfigurationsBits in the NSACR, see Non-Secure Access Control Register onpage 4-65, control Non-secure access to the CPACR fields.Attributes See the register summary in Table 4-3 on page 4-5.Figure 4-25 shows the CPACR bit assignments.31 3024 23 22 21 20 19 0Reserved cp11 cp10 ReservedASEDISFigure 4-25 CPACR bit assignmentsARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-62ID062913Non-Confidential