ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control• The L2 internal asynchronous error and AXI asynchronous errorbits of the L2ECTLR, see L2 Extended Control Register onpage 4-87.• The ASEDIS bit of the CPACR, see Coprocessor Access ControlRegister on page 4-62.Usage constraints The NSACR is:• Only accessible from PL1 or higher, with access rights that dependon the mode and security state:— Read/write in Secure PL1 modes.— Read-only in Non-secure PL1 and PL2 modes.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-3 on page 4-5.Figure 4-27 shows the NSACR bit assignments.31 19 18 17 16 15 14 12 11 10 9 0ReservedReservedNS_SMPNS_L2ERRReservedNSASEDISReservedcp11cp10Figure 4-27 NSACR bit assignmentsTable 4-56 shows the NSACR bit assignments.Table 4-56 NSACR bit assignmentsBits Name Function[31:20] - Reserved, UNK/SBZP.[19] - Reserved, RAZ/WI.[18] NS_SMP Determines if the SMP bit of the Auxiliary Control Register, see Auxiliary Control Register onpage 4-57, is writable in Non-secure state:0 A write to ACTLR in Non-secure state is ignored. This is the reset value.1 A write to ACTLR in Non-secure state can modify the value of the SMP bit. Otherbits in the ACTLR are write-ignored.[17] NS_L2ERR Determines if the L2 internal asynchronous error and AXI asynchronous error bits of the L2Extended Control Register, see L2 Extended Control Register on page 4-87, are writable inNon-secure state:0 A write to L2ECTLR in Non-secure state is ignored. This is the reset value.1 A write to L2ECTLR in Non-secure state can modify the value of the L2 internalasynchronous error and AXI asynchronous error bits. Other bits in the L2ECTLRare write-ignored.[16] - Reserved.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-66ID062913Non-Confidential