ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlMCR p15, 4, , c0, c0, 5; Write Virtualization Multiprocessor ID Register4.3.27 System Control RegisterThe SCTLR characteristics are:PurposeProvides the top level control of the system, including its memory system.Usage constraints The SCTLR:• Is a read/write register.• Banked for Secure and Non-secure states for all implemented bits.• Is only accessible from PL1 or higher.• Has write access to the Secure copy of the register disabled when theCP15SDISABLE signal is asserted HIGH. Attempts to write to thisregister in Secure PL1 modes when CP15SDISABLE is HIGHresult in an Undefined Instruction exception.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-3 on page 4-5.Figure 4-23 shows the SCTLR bit assignments.31 30 29 28 27 26 25 24 21 20 19 18 14 13 12 11 10 93 2 1 0ReservedV I Z Reserved C AMWXNUWXNReservedSWEEReservedTREAFETEReservedFigure 4-23 SCTLR bit assignmentsARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-54ID062913Non-Confidential