ARM Cortex-A15 MPCore Processor Technical Reference Manual

Level 2 Memory System7.5 Cache coherencyThe SCU uses hybrid Modified Exclusive Shared Invalid (MESI) and Modified OwnedExclusive Shared Invalid (MOESI) protocols to maintain coherency between the individual L1data caches and the L2 cache. The L1 data caches support the MESI protocol. The L2 memorysystem contains a snoop tag array that is a duplicate copy of each of the L1 data cachedirectories. The snoop tag array reduces the amount of snoop traffic between the L2 memorysystem and the L1 memory system. Any line that resides in the snoop tag array in theModified/Exclusive state belongs to the L1 memory system. Any access that hits against a linein this state must be serviced by the L1 memory system and passed to the L2 memory system.If the line is invalid or in the shared state in the snoop tag array, then the L2 cache can supplythe data.The SCU contains buffers that can handle direct cache-to-cache transfers between cores withoutreading or writing any data on the ACE. Lines can migrate back and forth without any changeto the MOESI state of the line in the L2 cache.Shareable transactions on the ACP are also coherent, so the snoop tag arrays are queried as aresult of ACP transactions. For reads where the shareable line resides in one of the L1 datacaches in the Modified/Exclusive state, the line is transferred from the L1 memory system to theL2 memory system and passed back on the ACP.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 7-10ID062913Non-Confidential