ARM Cortex-A15 MPCore Processor Technical Reference Manual

PrefaceThis preface introduces the ARM ® Cortex ® -A15 MPCore Processor Technical ReferenceManual. It contains the following sections:• About this book on page vii.• Feedback on page xi.Note• The out-of-order design of the Cortex-A15 MPCore processor pipeline makes itimpossible to provide accurate timing information for complex instructions. The timingof an instruction can be affected by factors such as:— Other concurrent instructions.— Memory system activity.— Events outside the instruction flow.• Timing information has been provided in the past for some ARM processors to assist indetailed hand tuning of performance critical code sequences or in the development of aninstruction scheduler within a compiler. This timing information is not required forproducing optimized instruction sequences on the Cortex-A15 MPCore processor. Theout-of-order pipeline of the Cortex-A15 MPCore processor can schedule and execute theinstructions in an optimal fashion without any instruction reordering required.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. viID062913Non-Confidential