ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-76 shows the ACTLR2 bit assignments.Bits Name FunctionTable 4-76 Auxiliary Control Register 2 bit assignments[31] Enable CPU regional clock gates Enable CPU regional clock gates:0 Disables the CPU regional clock gates. When this bit iscleared, the regional clock gate enable is tied HIGH. This isthe reset value.1 Enables the CPU regional clock gates for additional clockgating. When this bit is set, the regional clock gates cangate-off the clock and potentially reduce dynamic powerdissipation.[30:1] - Reserved.[0] Execute data cache clean as data cacheclean/invalidateExecute data cache clean as data cache clean and invalidate:0 Normal behavior, executes data cache clean as data cacheclean. This is the reset value.1 Executes data cache clean as data cache clean andinvalidate.To access the ACTLR2, read or write the CP15 register with:MRC p15, 1, , c15, c0, 4; Read Auxiliary Control Register 2MCR p15, 1, , c15, c0, 4; Write Auxiliary Control Register 24.3.63 Configuration Base Address RegisterThe CBAR characteristics are:PurposeHolds the physical base address of the memory-mapped InterruptController registers.Usage constraints The CBAR is:• A read-only register.• Common to the Secure and Non-secure states.• Only accessible from PL1 or higher.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-14 on page 4-13.Figure 4-62 shows the CBAR bit assignments.31 15 148 7 0PERIPHBASE[31:15]ReservedPERIPHBASE[39:32]Figure 4-62 CBAR bit assignmentsARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-106ID062913Non-Confidential