ARM Cortex-A15 MPCore Processor Technical Reference Manual

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System ControlTable 4-22 Address translation operations (continued)Name CRn Op1 CRm Op2 Reset Width DescriptionATS12NSOUW 7 UNK 32-bit Stages 1 and 2 Non-secure unprivileged write, see theARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionATS1HR 4 c8 0 UNK 32-bit Stage 1 Hyp mode read, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionATS1HW 1 UNK 32-bit Stage 1 Hyp mode write, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition4.2.23 Miscellaneous operationsTable 4-23 shows the 32-bit wide miscellaneous operations.Table 4-23 Miscellaneous system control operationsName CRn Op1 CRm Op2 Reset DescriptionNOP c7 0 c0 4 UNK System control No Operation (NOP), see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionCP15ISB c5 4 UNK Instruction Synchronization Barrier operation, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-R editionCP15DSB c10 4 UNK Data Synchronization Barrier operation, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionCP15DMB 5 UNK Data Memory Barrier operation, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionNOP c13 1 UNK System control No Operation (NOP), see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionTPIDRURW c13 0 c0 2 UNK User Read/Write Thread ID Register, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionTPIDRURO 3 UNK User Read-Only Thread ID Register, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionTPIDRPRW 4 UNK PL1 only Thread ID Register, see the ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R editionHTPIDR 4 c0 2 UNK Hyp Software Thread ID Register, see the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R editionARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-20ID062913Non-Confidential
System Control4.2.24 Performance monitor registersTable 4-24 shows the 32-bit wide performance monitor registers.Name CRn Op1 CRm Op2 Reset DescriptionTable 4-24 Performance monitor registersPMCR c9 0 c12 0 0x410F3000 Performance Monitor Control Register on page 11-8PMNCNTENSET 1 UNK Performance Monitor Count Enable Set Register, see theARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionPMNCNTENCLR 2 UNK Performance Monitor Count Enable Clear Register, see theARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionPMOVSR 3 UNK Performance Monitor Overflow Flag Status Register, see theARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionPMSWINC 4 UNK Performance Monitor Software Increment Register, see theARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionPMSELR 5 UNK Performance Monitor Event Counter Selection Register, seethe ARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionPMCEID0 6 0x3FFF0F3F Performance Monitor Common Event Identification Register0 on page 11-10PMCEID1 7 0x00000000 Performance Monitor Common Event Identification Register1 on page 11-12PMCCNTR c13 0 UNK Performance Monitor Cycle Count Register, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-ReditionPMXEVTYPER 1 UNK Performance Monitor Event Type Select Register, see theARM ® Architecture Reference Manual ARMv7-A andARMv7-R editionPMXEVCNTR 2 UNK Performance Monitor Event Count Register, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-ReditionPMUSERENR c14 0 0x00000000 Performance Monitor User Enable Register, see the ARM ®Architecture Reference Manual ARMv7-A and ARMv7-ReditionARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-21ID062913Non-Confidential
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®ARM®Cortex -A15 MPCoreProcessorR
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ContentsARM Cortex-A15 MPCore Proce
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Contents11.4 PMU register descripti
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PrefaceAbout this bookThis book is
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Preface(continued)Stylemonospace bo
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PrefaceFeedbackARM welcomes feedbac
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Introduction1.1 About the Cortex-A1
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Introduction1.2.3 Debug architectur
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Introduction1.4 InterfacesThe proce
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Introduction• The L2 tag RAM regi
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IntroductionThe ARM product deliver
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Introduction1.7.5 r1p0 - r2p0The fo
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Introduction• Added L1 data TLB s
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Functional Description2.1 About the
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Functional DescriptionLoad/Store un
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Functional Description2.2 Interface
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Functional Description2.3 Clocking
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Functional DescriptionFigure 2-5 sh
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Functional DescriptionAll resets ar
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Functional DescriptionPowerup reset
Page 43 and 44: Functional Description• nPRESETDB
Page 45 and 46: Functional Description• L2 unifie
Page 47 and 48: Functional DescriptionOn entry into
Page 49 and 50: Functional DescriptionWhen the proc
Page 51 and 52: Functional DescriptionNoteFigure 2-
Page 53 and 54: Functional DescriptionRegional cloc
Page 55 and 56: Functional DescriptionTable 2-3 Val
Page 57 and 58: Functional Description4. Release th
Page 59 and 60: Functional DescriptionDebug power d
Page 61 and 62: Functional DescriptionNoteAfter a p
Page 63 and 64: Functional DescriptionThe external
Page 65 and 66: Programmers Model3.1 About the prog
Page 67 and 68: Programmers Model3.3 Advanced SIMD
Page 69 and 70: Programmers ModelYou can use the CP
Page 71 and 72: Programmers Model3.6 Large Physical
Page 73 and 74: Programmers Model3.8 Modes of opera
Page 75 and 76: Chapter 4System ControlThis chapter
Page 77 and 78: System Control4.2 Register summaryT
Page 79 and 80: System ControlOp1 CRm Op2 Name Rese
Page 81 and 82: System ControlTable 4-6 c5 register
Page 83 and 84: System ControlTable 4-8 c7 register
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Page 87 and 88: System Control4.2.14 c15 registersT
Page 89 and 90: System ControlName CRn Op1 CRm Op2
Page 91 and 92: System Control4.2.19 Other system c
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Page 97 and 98: System Control4.2.26 Virtualization
Page 99 and 100: System ControlName CRn Op1 CRm Op2
Page 101 and 102: System Control4.3 Register descript
Page 103 and 104: System ControlTo access the CTR, re
Page 106 and 107: System ControlTable 4-34 shows the
Page 110 and 111: System Control4.3.12 Memory Model F
Page 114 and 115: System ControlTable 4-40 ID_MMFR3 b
Page 116 and 117: System Control31 28 27 24 23 20 19
Page 118 and 119: System ControlTable 4-43 ID_ISAR2 b
Page 126 and 127: System ControlConfigurationsAvailab
Page 128 and 129: System ControlMCR p15, 4, , c0, c0,
Page 130 and 131: System ControlTable 4-52 SCTLR bit
Page 134 and 135: System ControlTable 4-53 ACTLR bit
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System ControlTable 4-58 shows the
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System ControlUsage constraints The
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System ControlTable 4-59 HCPTR bit
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System ControlTable 4-61 DFSR bit a
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System ControlTable 4-63 IFSR bit a
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System ControlConfigurationsAvailab
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System Control• UNKNOWN when exec
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System Control31 30 26 25 24 23 22
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System Control• Only accessible f
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System Control31 0DataFigure 4-40 I
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System ControlThe data returned fro
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System ControlThe data returned fro
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System Control31 24 23 21 20 19 18
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System Control4.3.60 L2 Auxiliary C
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System ControlTable 4-74 L2ACTLR bi
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System Control• Is only accessibl
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System ControlTable 4-79 L2MERRSR b
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Memory Management Unit5.1 About the
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Memory Management Unit5.3 TLB match
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Memory Management Unit• The TLB t
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Memory Management Unit5.6 Intermedi
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Memory Management Unit5.7 External
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Level 1 Memory System6.1 About the
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Level 1 Memory System6.3 L1 instruc
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Level 1 Memory System6.4 L1 data me
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Level 1 Memory SystemL1 or L2 cache
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Level 1 Memory SystemExternal globa
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Level 1 Memory System6.5 Program fl
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Level 1 Memory SystemReset:• Disa
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Chapter 7Level 2 Memory SystemThis
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Level 2 Memory System7.2 Cache orga
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Level 2 Memory System7.2.5 Register
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Level 2 Memory SystemNote• The L2
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Level 2 Memory System7.4 L2 cache p
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Level 2 Memory System7.6 Asynchrono
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Level 2 Memory SystemFor certain tr
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Level 2 Memory System7.7.6 Snoop fi
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Level 2 Memory SystemTable 7-6 show
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Chapter 8Generic Interrupt Controll
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Generic Interrupt Controller8.2 GIC
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Generic Interrupt Controller8.2.4 I
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Generic Interrupt Controller8.3 GIC
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Generic Interrupt ControllerOffset
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Generic Interrupt ControllerTable 8
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Generic Interrupt ControllerPrivate
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Generic Interrupt Controller0x1D043
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Generic Interrupt ControllerThe Cor
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Generic Interrupt ControllerTable 8
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Generic Interrupt Controller8.3.8 V
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Generic Timer9.1 About the Generic
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Generic Timer9.3 Generic Timer prog
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Chapter 10DebugThis chapter describ
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Debug• Operating systems.• Hard
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DebugnPRESETDBGThis signal initiali
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DebugTable 10-1 CP14 debug register
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DebugTable 10-1 CP14 debug register
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DebugTable 10-2 DBGDIDR bit assignm
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DebugTable 10-4 shows the DBGDRCR b
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DebugConfigurationsAttributesThe pr
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DebugTable 10-8 DBGBCR bit assignme
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DebugTable 10-10 shows the DBGWCR b
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Debug31 12 11 2 1 0ROMADDR[31:12]Re
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Debug10.4.12 OS Lock Status Registe
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DebugTable 10-15 shows the DBGPRCR
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DebugTable 10-16 DBGDSAR bit assign
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Debug31 1 0ReservedIntegration mode
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DebugTable 10-22 shows the DBGDEVID
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Debug10.4.23 Component Identificati
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Debug10.6 External debug interfaceT
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DebugIf software running on the pro
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Performance Monitor Unit11.1 About
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Performance Monitor Unit11.3 PMU re
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Performance Monitor UnitTable 11-1
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Performance Monitor Unit11.5 Effect
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Performance Monitor Unit11.7 Interr
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Chapter 12Program Trace MacrocellTh
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Program Trace Macrocell12.2 PTM opt
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Program Trace MacrocellYou can also
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Program Trace Macrocell12.5 PTM pro
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Program Trace Macrocellarchitecture
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Program Trace Macrocell12.6 Registe
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Program Trace MacrocellTable 12-4 P
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Program Trace MacrocellTable 12-5 E
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Program Trace MacrocellTable 12-6 E
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Program Trace Macrocell31 26 25 24
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Program Trace Macrocell12.7.8 Confi
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Program Trace Macrocell12.7.10 Auxi
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Program Trace Macrocell31 4 3 2 0Re
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Program Trace MacrocellTable 12-17
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Program Trace Macrocell31 7 60Reser
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Program Trace MacrocellThe Componen
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Cross Trigger13.1 About the cross t
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Cross Trigger13.3 Cortex-A15 CTIIn
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Chapter 14NEON and VFP UnitThis cha
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NEON and VFP UnitARM DDI 0438I Copy
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NEON and VFP UnitSee the ARM ® Arc
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NEON and VFP UnitConfigurationsAvai
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NEON and VFP UnitTable 14-5 FPSCR b
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NEON and VFP UnitTable 14-6 MVFR1 b
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NEON and VFP Unit31 30 29 0Reserved
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Signal DescriptionsA.1 About the si
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Signal DescriptionsA.3 Reset signal
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Signal DescriptionsA.5 Generic Inte
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Signal DescriptionsA.6 Generic Time
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Signal DescriptionsA.8 Power manage
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Signal DescriptionsA.9 AXI interfac
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Signal DescriptionsWrite address ch
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Signal DescriptionsTable A-14 Read
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Signal DescriptionsTable A-20 Write
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Signal DescriptionsA.10 External de
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Signal DescriptionsTable A-27 Misce
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Signal DescriptionsA.12 Cross trigg
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Signal DescriptionsA.14 DFT and MBI
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Appendix BRevisionsThis appendix de
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RevisionsTable B-3 Differences betw
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