ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-53 ACTLR bit assignments (continued)Bits Name Function[18] a Disable L2 stage 1 translation tablewalk L2 PA cache[17] a Disable L2 TLB performanceoptimization[16] a Enable full Strongly-ordered andDevice load replay[15] a Force in-order issue in branchexecution unit[14] a Force limit of one instruction groupcommit/de-allocate per cycleDisables L2 stage 1 translation table walk L2 PA cache:0 Enables L2 stage 1 translation table walk L2 PA cache. This isthe reset value.1 Disables L2 stage 1 translation table walk L2 PA cache.Disables L2 TLB performance optimization:0 Enables L2 TLB optimization. This is the reset value.1 Disables L2 TLB optimization.Enables full Strongly-ordered and Device load replay:0 Disables full Strongly-ordered and Device load replay. This isthe reset value.1 Enables full Strongly-ordered and Device load replay.Forces in-order issue in branch execution unit:0 Disables forced in-order issue. This is the reset value.1 Forces in-order issue.Forces limit of one instruction group to commit and de-allocate per cycle:0 Normal commit and de-allocate behavior. This is the resetvalue.1 Limits commit and de-allocate to one instruction group percycle.[13] a Flush after CP14, CP15 writes Flushes after certain CP14 and CP15 writes:0 Normal behavior for CP14 and CP15 writes. This is the resetvalue.1 Flushes after certain CP14 and CP15 writes.[12] a Force push of CP14 and CP15 registers Forces push of certain CP14 and CP15 registers from local dispatch copies toshadow copies:0 Normal behavior for CP14 and CP15 instructions. This is thereset value.1 Pushes certain CP14 and CP15 registers from local dispatchcopies to shadow copies.NoteSetting this bit to 1 forces the processor to behave as if bit[13] is set to 1.[11] a Limit to one instruction per instructiongroup[10] a Force serialization after eachinstruction groupLimits to one instruction per instruction group:0 Normal instruction grouping. This is the reset value.1 Limits to one instruction per instruction group.Forces serialization after each instruction group:0 Disables forced serialization after each instruction group. Thisis the reset value.1 Forces serialization after each instruction group.NoteSetting this bit to 1 forces the processor to behave as if bit[11] is set to 1.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-60ID062913Non-Confidential