ARM Cortex-A15 MPCore Processor Technical Reference Manual

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Performance Monitor Unit11.3 PMU register summaryThe PMU counters and their associated control registers are accessible from the internal CP15interface and from the Debug APB interface.Table 11-1 gives a summary of the Cortex-A15 PMU registers.Table 11-1 PMU register summaryRegisternumberOffset CRn Op1 CRm Op2 Name Type Description0 0x000 c9 0 c13 2 PMXEVCNTR0 RW Event Count Register, see the ARM ®1 0x004 c9 0 c13 2 PMXEVCNTR1 RWArchitecture Reference ManualARMv7-A and ARMv7-R edition2 0x008 c9 0 c13 2 PMXEVCNTR2 RW3 0x00C c9 0 c13 2 PMXEVCNTR3 RW4 0x010 c9 0 c13 2 PMXEVCNTR4 RW5 0x014 c9 0 c13 2 PMXEVCNTR5 RW6-30 0x018-0x78 - - - - - - Reserved31 0x07C c9 0 c13 0 PMCCNTR RW Cycle Count Register, see the ARM ®Architecture Reference ManualARMv7-A and ARMv7-R edition32-255 0x080-0x3FC - - - - - Reserved256 0x400 c9 0 c13 1 PMXEVTYPER0 RW Event Type Select Register, see the257 0x404 c9 0 c13 1 PMXEVTYPER1 RWARM ® Architecture ReferenceManual ARMv7-A and ARMv7-R258 0x408 c9 0 c13 1 PMXEVTYPER2 RWedition259 0x40C c9 0 c13 1 PMXEVTYPER3 RW260 0x410 c9 0 c13 1 PMXEVTYPER4 RW261 0x414 c9 0 c13 1 PMXEVTYPER5 RW262-286 0x418-0x478 - - - - - - Reserved287 0x47C c9 0 c13 1 PMXEVTYPER31 RW Performance Monitors Event TypeSelect Register 31, see the ARM ®Architecture Reference ManualARMv7-A and ARMv7-R edition288-767 0x480-0xBFC - - - - - - Reserved768 0xC00 c9 0 c12 1 PMCNTENSET RW Count Enable Set Register, see theARM ® Architecture ReferenceManual ARMv7-A and ARMv7-Redition769-775 0xC04-0xC1C - - - - - - Reserved776 0xC20 c9 0 c12 2 PMCNTENCLR RW Count Enable Clear Register, see theARM ® Architecture ReferenceManual ARMv7-A and ARMv7-Redition777-783 0xC24-0xC3C - - - - - - ReservedARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 11-4ID062913Non-Confidential
Performance Monitor UnitTable 11-1 PMU register summary (continued)RegisternumberOffset CRn Op1 CRm Op2 Name Type Description784 0xC40 c9 0 c14 1 PMINTENSET RW Interrupt Enable Set Register, seethe ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-Redition785-791 0xC44-0xC5C - - - - - - Reserved792 0xC60 c9 0 c14 2 PMINTENCLR RW Interrupt Enable Clear Register, seethe ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-Redition793-799 0xC64-0xC7C - - - - - - Reserved800 0xC80 c9 0 c12 3 PMOVSR RW Overflow Flag Status Register, seethe ARM ® Architecture ReferenceManual ARMv7-A and ARMv7-Redition801-807 0xC84-0xC9C - - - - - - Reserved808 0xCA0 c9 0 c12 4 PMSWINC WO Software Increment Register, see theARM ® Architecture ReferenceManual ARMv7-A and ARMv7-Redition809-815 0xCA4-0xCBC - - - - - - Reserved816 0xCC0 c9 0 c14 3 PMOVSSET RW Performance Monitor OverflowStatus Set Register, see the ARM®Architecture Reference ManualARMv7-A and ARMv7-R edition817-895 0xCC4-0xDFC - - - - - - Reserved896 0xE00 - - - - PMCFGR RO Performance MonitorConfiguration Register onpage 11-7897 0xE04 c9 0 c12 0 PMCR RW Performance Monitor ControlRegister on page 11-8898 0xE08 c9 0 c14 0 PMUSERENR RW User Enable Register, see the ARM ®Architecture Reference ManualARMv7-A and ARMv7-R edition899-903 0xE0C-0xE1C - - - - - - Reserved904 0xE20 c9 0 c12 6 PMCEID0 RO Common Event IdentificationRegister 0 bit assignments onpage 11-11905 0xE24 c9 0 c12 7 PMCEID1 RO Performance Monitor CommonEvent Identification Register 1 onpage 11-12906-1003 0xE28-0xFAC - - - - - - ReservedARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 11-5ID062913Non-Confidential
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®ARM®Cortex -A15 MPCoreProcessorR
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ContentsARM Cortex-A15 MPCore Proce
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Contents11.4 PMU register descripti
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PrefaceAbout this bookThis book is
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Preface(continued)Stylemonospace bo
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PrefaceFeedbackARM welcomes feedbac
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Introduction1.1 About the Cortex-A1
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Introduction1.2.3 Debug architectur
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Introduction1.4 InterfacesThe proce
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Introduction• The L2 tag RAM regi
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IntroductionThe ARM product deliver
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Introduction1.7.5 r1p0 - r2p0The fo
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Introduction• Added L1 data TLB s
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Functional Description2.1 About the
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Functional DescriptionLoad/Store un
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Functional Description2.2 Interface
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Functional Description2.3 Clocking
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Functional DescriptionFigure 2-5 sh
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Functional DescriptionAll resets ar
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Functional DescriptionPowerup reset
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Functional Description• nPRESETDB
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Functional Description• L2 unifie
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Functional DescriptionOn entry into
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Functional DescriptionWhen the proc
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Functional DescriptionNoteFigure 2-
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Functional DescriptionRegional cloc
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Functional DescriptionTable 2-3 Val
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Functional Description4. Release th
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Functional DescriptionDebug power d
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Functional DescriptionNoteAfter a p
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Functional DescriptionThe external
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Programmers Model3.1 About the prog
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Programmers Model3.3 Advanced SIMD
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Programmers ModelYou can use the CP
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Programmers Model3.6 Large Physical
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Programmers Model3.8 Modes of opera
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Chapter 4System ControlThis chapter
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System Control4.2 Register summaryT
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System ControlOp1 CRm Op2 Name Rese
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System ControlTable 4-6 c5 register
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System ControlTable 4-8 c7 register
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System ControlTable 4-10 c9 registe
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System Control4.2.14 c15 registersT
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System ControlName CRn Op1 CRm Op2
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System Control4.2.19 Other system c
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System Control4.2.24 Performance mo
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System Control4.2.26 Virtualization
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System Control4.3 Register descript
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System ControlTo access the CTR, re
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System ControlTable 4-34 shows the
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System Control4.3.12 Memory Model F
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System ControlTable 4-40 ID_MMFR3 b
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System Control31 28 27 24 23 20 19
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System ControlTable 4-43 ID_ISAR2 b
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System ControlConfigurationsAvailab
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System ControlMCR p15, 4, , c0, c0,
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System ControlTable 4-52 SCTLR bit
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System Control31 30 29 28 27 26 25
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System ControlTable 4-53 ACTLR bit
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System ControlTable 4-53 ACTLR bit
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System ControlUsage constraints The
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System Control• The L2 internal a
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System Control31 30 29 28 27 26 25
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System ControlUsage constraints The
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System ControlTable 4-59 HCPTR bit
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System ControlTable 4-61 DFSR bit a
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System ControlTable 4-63 IFSR bit a
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System ControlConfigurationsAvailab
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System Control• UNKNOWN when exec
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System Control31 30 26 25 24 23 22
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System Control• Only accessible f
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System Control31 0DataFigure 4-40 I
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System ControlThe data returned fro
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System ControlThe data returned fro
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System Control31 24 23 21 20 19 18
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System Control4.3.60 L2 Auxiliary C
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System ControlTable 4-74 L2ACTLR bi
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System Control• Is only accessibl
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System ControlTable 4-79 L2MERRSR b
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Memory Management Unit5.1 About the
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Memory Management Unit5.3 TLB match
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Memory Management Unit• The TLB t
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Memory Management Unit5.6 Intermedi
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Memory Management Unit5.7 External
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Level 1 Memory System6.1 About the
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Level 1 Memory System6.3 L1 instruc
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Level 1 Memory System6.4 L1 data me
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Level 1 Memory SystemL1 or L2 cache
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Level 1 Memory SystemExternal globa
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Level 1 Memory System6.5 Program fl
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Level 1 Memory SystemReset:• Disa
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Chapter 7Level 2 Memory SystemThis
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Level 2 Memory System7.2 Cache orga
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Level 2 Memory System7.2.5 Register
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Level 2 Memory SystemNote• The L2
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Level 2 Memory System7.4 L2 cache p
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Level 2 Memory System7.6 Asynchrono
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Level 2 Memory SystemFor certain tr
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Level 2 Memory System7.7.6 Snoop fi
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Level 2 Memory SystemTable 7-6 show
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Chapter 8Generic Interrupt Controll
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Generic Interrupt Controller8.2 GIC
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Generic Interrupt Controller8.2.4 I
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Generic Interrupt Controller8.3 GIC
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Generic Interrupt ControllerOffset
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Generic Interrupt ControllerTable 8
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Generic Interrupt ControllerPrivate
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Generic Interrupt Controller0x1D043
Page 244 and 245: Generic Interrupt ControllerThe Cor
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Page 250 and 251: Generic Timer9.1 About the Generic
Page 252 and 253: Generic Timer9.3 Generic Timer prog
Page 254 and 255: Chapter 10DebugThis chapter describ
Page 256 and 257: Debug• Operating systems.• Hard
Page 258 and 259: DebugnPRESETDBGThis signal initiali
Page 260 and 261: DebugTable 10-1 CP14 debug register
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Page 264 and 265: DebugTable 10-2 DBGDIDR bit assignm
Page 266 and 267: DebugTable 10-4 shows the DBGDRCR b
Page 268 and 269: DebugConfigurationsAttributesThe pr
Page 270 and 271: DebugTable 10-8 DBGBCR bit assignme
Page 272 and 273: DebugTable 10-10 shows the DBGWCR b
Page 274 and 275: Debug31 12 11 2 1 0ROMADDR[31:12]Re
Page 276 and 277: Debug10.4.12 OS Lock Status Registe
Page 278 and 279: DebugTable 10-15 shows the DBGPRCR
Page 280 and 281: DebugTable 10-16 DBGDSAR bit assign
Page 282 and 283: Debug31 1 0ReservedIntegration mode
Page 284 and 285: DebugTable 10-22 shows the DBGDEVID
Page 286 and 287: Debug10.4.23 Component Identificati
Page 288 and 289: Debug10.6 External debug interfaceT
Page 290 and 291: DebugIf software running on the pro
Page 292 and 293: Performance Monitor Unit11.1 About
Page 296 and 297: Performance Monitor UnitTable 11-1
Page 304 and 305: Performance Monitor Unit11.5 Effect
Page 308 and 309: Performance Monitor Unit11.7 Interr
Page 310 and 311: Chapter 12Program Trace MacrocellTh
Page 312 and 313: Program Trace Macrocell12.2 PTM opt
Page 314 and 315: Program Trace MacrocellYou can also
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Page 318 and 319: Program Trace Macrocellarchitecture
Page 320 and 321: Program Trace Macrocell12.6 Registe
Page 322 and 323: Program Trace MacrocellTable 12-4 P
Page 324 and 325: Program Trace MacrocellTable 12-5 E
Page 326 and 327: Program Trace MacrocellTable 12-6 E
Page 328 and 329: Program Trace Macrocell31 26 25 24
Page 330 and 331: Program Trace Macrocell12.7.8 Confi
Page 332 and 333: Program Trace Macrocell12.7.10 Auxi
Page 334 and 335: Program Trace Macrocell31 4 3 2 0Re
Page 336 and 337: Program Trace MacrocellTable 12-17
Page 338 and 339: Program Trace Macrocell31 7 60Reser
Page 340 and 341: Program Trace MacrocellThe Componen
Page 342 and 343: Cross Trigger13.1 About the cross t
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Cross Trigger13.3 Cortex-A15 CTIIn
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Chapter 14NEON and VFP UnitThis cha
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NEON and VFP UnitARM DDI 0438I Copy
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NEON and VFP UnitSee the ARM ® Arc
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NEON and VFP UnitConfigurationsAvai
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NEON and VFP UnitTable 14-5 FPSCR b
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NEON and VFP UnitTable 14-6 MVFR1 b
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NEON and VFP Unit31 30 29 0Reserved
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Signal DescriptionsA.1 About the si
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Signal DescriptionsA.3 Reset signal
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Signal DescriptionsA.5 Generic Inte
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Signal DescriptionsA.6 Generic Time
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Signal DescriptionsA.8 Power manage
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Signal DescriptionsA.9 AXI interfac
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Signal DescriptionsWrite address ch
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Signal DescriptionsTable A-14 Read
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Signal DescriptionsTable A-20 Write
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Signal DescriptionsA.10 External de
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Signal DescriptionsTable A-27 Misce
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Signal DescriptionsA.12 Cross trigg
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Signal DescriptionsA.14 DFT and MBI
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Appendix BRevisionsThis appendix de
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RevisionsTable B-3 Differences betw
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ARM Cortex-A15 MPCore Processor Technical Reference Manual

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