ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0Innermost shareabilityFCSE supportAuxiliary registersTCM supportShareability levelsOutermost shareabilityPMSA supportVMSA supportTable 4-37 shows the ID_MMFR0 bit assignments.Figure 4-9 ID_MMFR0 bit assignmentsTable 4-37 ID_MMFR0 bit assignmentsBits Name Function[31:28] Innermost shareability Indicates the innermost shareability domain implemented:0x1Processor implements hardware coherency support.[27:24] FCSE Indicates support for Fast Context Switch Extension (FCSE):0x0Processor does not support FCSE.[23:20] Auxiliary registers Indicates support for Auxiliary registers:0x2Processor supports the ACTLR and ADFSR. See Auxiliary Control Register onpage 4-57 and Auxiliary Data Fault Status Register on page 4-81.[19:16] TCM Indicates support for TCMs and associated DMAs:0x0Processor does not support TCM.[15:12] Shareability levels Indicates the number of shareability levels implemented:0x1Processor implements two levels of shareability.[11:8] Outermost shareability Indicates the outermost shareability domain implemented:0x1Processor supports hardware coherency.[7:4] PMSA Indicates support for a Protected Memory System Architecture (PMSA):0x0Processor does not support PMSA.[3:0] VMSA Indicates support for a Virtual Memory System Architecture (VMSA).0x5Processor supports:• VMSAv7, with support for remapping and the Access flag.• Privileged Execute Never (PXN) bit in the Short-descriptor translationtable format.• Privileged Execute Never (PXN) bit in the Long-descriptor translationtable format.To access the ID_MMFR0, read the CP15 register with:MRC p15, 0, , c0, c1, 4; Read Memory Model Feature Register 0ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-35ID062913Non-Confidential