ARM Cortex-A15 MPCore Processor Technical Reference Manual

Memory Management Unit5.2 TLB organizationThe Cortex-A15 MPCore processor implements a 2-level TLB structure. The TLBs, at eitherthe L1 or the L2 level, do not require to be flushed on a context or virtual machine switch. TheCortex-A15 MMU does not support the locking of TLB entries at either Level 1 or Level 2.This section describes the TLB organization in:• L1 instruction TLB.• L1 data TLB.• L2 TLB.5.2.1 L1 instruction TLBThe L1 instruction TLB is a 32-entry fully-associative structure. This TLB caches entries at the4KB granularity of Virtual Address (VA) to Physical Address (PA) mapping only. If the pagetables map the memory region to a larger granularity than 4K, it only allocates one mapping forthe particular 4K region to which the current access corresponds.A hit in the instruction TLB provides a single CLK cycle access to the translation, and returnsthe physical address to the instruction cache for comparison. It also checks the accesspermissions to signal a Prefetch Abort.5.2.2 L1 data TLBThere are two separate 32-entry fully-associative TLBs that are used for data loads and stores,respectively. Similar to the L1 instruction TLB, both of these cache entries at the 4KBgranularity of VA to PA mappings only.At implementation time, the Cortex-A15 MPCore processor can be configured with the-l1tlb_1m option, to have the L1 data TLB cache entries at both the 4KB and 1MB granularity.With this configuration, any translation that results in a 1MB or larger page is cached in the L1data TLB as a 1MB entry. Any translation that results in a page smaller than 1MB is cached inthe L1 data TLB as a 4KB entry. By default, all translations are cached in the L1 data TLB as a4KB entry.A hit in the data load or store TLBs provides a single CLK cycle access to the translation, andreturns the physical address to the instruction cache for comparison. It also checks the accesspermissions to signal a Data Abort.5.2.3 L2 TLBMisses from the L1 instruction and data TLBs are handled by a unified L2 TLB. This is a512-entry 4-way set-associative structure. The L2 TLB supports all the VMSAv7 page sizes of4K, 64K, 1MB and 16MB in addition to the LPAE page sizes of 2MB and 1GB.Accesses to the L2 TLB take a variable number of cycles, based on the competing requests fromeach of the L1 TLBs, TLB maintenance operations in flight, and the different page sizemappings in use.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 5-3ID062913Non-Confidential