ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-59 shows the HCPTR bit assignments.Table 4-59 HCPTR bit assignmentsBits Name Function[31] TCPAC Trap Coprocessor Access Control Register accesses:0 Has no effect on CPACR accesses.1 Trap valid Non-secure PL1 CPACR accesses to Hyp mode.When this bit is set to 1, any valid Non-secure PL1 or PL0 access to the CPACR is trapped to Hypmode. See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition for moreinformation.[30:16] - Reserved, UNK/SBZP.[15] TASE Trap Advanced SIMD Extension use:0 If the NSACR settings permit Non-secure use of the Advanced SIMDfunctionality then Hyp mode can access that functionality, regardless of anysettings in the CPACR.NoteThis bit value has no effect on possible use of the Advanced SIMD functionalityfrom Non-secure PL1 and PL0 modes.1 Trap valid Non-secure accesses to Advanced SIMD functionality to Hyp mode.When this bit is set to 1, any otherwise-valid access to Advanced SIMDfunctionality from:• A Non-secure PL1 or PL0 mode is trapped to Hyp mode.• Hyp mode generates an Undefined Instruction exception, taken in Hypmode.NoteIf TCP10 and TCP11 are set to 1, then all Advanced SIMD use is trapped to Hyp mode, regardlessof the value of this field.[14] - Reserved, RAZ/WI.[13:12] - Reserved, RAO/WI.If VFP is implemented and NEON is not implemented, this bit is RAO/WI.If VFP and NEON are not implemented, this bit is RAO/WI.If NSACR.NSASEDIS is set to 1, then on Non-secure accesses to the HCPTR, the TASE bitbehaves as RAO/WI.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-73ID062913Non-Confidential