ARM Cortex-A15 MPCore Processor Technical Reference Manual

Functional DescriptionTable 2-3 Valid power modes (continued)ModeProcessor a(CLK)NEON and VFP(CLK)Debug-APB,CTI, andCTM(PCLKDBG)L2 RAMs b(CLK)L2 control, IC,Timer (CLK)L2 RAMs retain with Debugpowered upPowered down Powered down Powered up Retention state Powered downDebug powered up Powered down Powered down Powered up Powered down Powered downL2 powered up Powered down Powered down Powered down Powered up Powered upL2 RAMs retain or dormantmodePowered down Powered down Powered down Retention state Powered downShutdown Powered down Powered down Powered down Powered down Powered downa. Processor logic, including Debug, PTM, breakpoint and watchpoint logic, but excluding NEON and VFP.b. L2 cache tag bank RAMs that include tag, dirty, data, and data ECC RAMs if ECC support is present.There are specific requirements that you must meet to power up and power down each powerdomain within the processor. Not adhering to these requirements can lead to UNPREDICTABLEresults.The powerup and powerdown sequences in the following sections are the only power sequencesthat ARM recommends. Any deviation from these sequences can lead to UNPREDICTABLEresults.The supported powerup and powerdown sequences are:• Processor power domain.• NEON and VFP power domain on page 2-32.• Debug power domain on page 2-34.• External debug over power down on page 2-34.• Dormant mode on page 2-35.• Processor powerdown mode on page 2-36.NoteThe powerup and powerdown sequences require that you isolate the powerup domain beforepower is removed from the powerdown domain. You must clamp the outputs of the powerdowndomain to benign values to prevent data corruption or UNPREDICTABLE behavior in the powerupdomain. The SoC controls the clamping using the nISOLATExx input pins.Processor power domainIf a processor is not required, you can reduce leakage power by turning off the power to theprocessor. The processor refers to all processor logic, including Debug, PTM, breakpoint andwatchpoint logic, but excluding the NEON and VFP unit. Powering down the processor requiresthat you also power down the NEON and VFP unit.To enable the processor to be powered down, the implementation must place the processor andNEON and VFP unit on separately controlled power supplies. In addition, you must clamp theoutputs of the processor and the NEON and VFP unit to benign values while the entire processoris powered down, to indicate that the processor is idle.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 2-30ID062913Non-Confidential