ARM Cortex-A15 MPCore Processor Technical Reference Manual

Signal DescriptionsA.2 Clock signalsSignal Type DescriptionCLK Input Global clock.Table A-1 shows the clock and clock enable signals.Table A-1 Clock and clock enable signalsCLKEN Input Global clock enable. This signal can only be deasserted with all the processors in the MPCoredevice and L2 are in WFI low-power state, and both the ACE and ACP are idle.CPUCLKOFF[N:0] a Input Individual processor clock disable.0 Processor clock is enabled.1 Processor clock is stopped.This signal is only present if the Cortex-A15 MPCore processor is configured with theCPUCLKOFF pins. The default configuration does not include the CPUCLKOFF pins. Thissignal can only be asserted when the processor is already powered down, or when the processoris powered up. To enable the powerup reset sequence to complete, this signal must be deassertedafter power has been completely restored. See Clocks on page 2-8 for more information.a. These signals are not available in revisions prior to r3p0.See Clocking and resets on page 2-8 for more information.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. A-3ID062913Non-Confidential