ARM Cortex-A15 MPCore Processor Technical Reference Manual

Debug10.2 Debug register interfacesThe processor implements the ARMv7.1 Debug architecture and debug events as described inthe ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition.The Debug architecture defines a set of debug registers. The debug register interfaces provideaccess to these registers from:• Software running on the processor, see Processor interfaces.• An external debugger, see External debug interface on page 10-35.This section describes:• Processor interfaces.• Breakpoints and watchpoints.• Effects of resets on debug registers.10.2.1 Processor interfaces10.2.2 Breakpoints and watchpointsThe processor has the following interfaces to the debug, performance monitor, and traceregisters:Debug registersThis interface is Baseline CP14, Extended CP14, and memory-mapped. You canaccess the debug register map using the APB slave port. See External debuginterface on page 10-35.Performance monitorThis interface is CP15 based and memory-mapped. You can access theperformance monitor registers using the APB slave port. See External debuginterface on page 10-35.Trace registersThis interface is memory-mapped. See External debug interface on page 10-35.The processor supports six hardware breakpoints, four watchpoints, and a standard DebugCommunications Channel (DCC). Four of the breakpoints match only to virtual address and theother two match against either virtual address or context ID, or Virtual Machine Identifier(VMID). All the watchpoints can be linked to two breakpoints to enable a memory request tobe trapped in a given process context.10.2.3 Effects of resets on debug registersThe processor has the following reset signals that affect the debug registers:nCPUPORESETThis signal initializes the processor logic, including the debug, Program TraceMacrocell (PTM), breakpoint, watchpoint logic, and performance monitors logic.nDBGRESETThis signal resets the debug and PTM logic in the processor CLK domain,including the breakpoint and watchpoint logic. Performance monitors logic is notaffected.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 10-4ID062913Non-Confidential