ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-48 shows the CLIDR bit assignments.Table 4-48 CLIDR bit assignmentsBits Name Function[31:30] - Reserved, RAZ.[29:27]] LoUU Indicates the Level of Unification Uniprocessor for the cache hierarchy:b001 L2 cache.[26:24] LoC Indicates the Level of Coherency for the cache hierarchy:b010 L3 cache.[23:21] LoUIS Indicates the Level of Unification Inner Shareable for the cache hierarchy:b001 L2 cache.[20:18] Ctype7 Indicates the type of cache implemented at level 7:b000 No cache.[17:15] Ctype6 Indicates the type of cache implemented at level 6:b000 No cache.[14:12] Ctype5 Indicates the type of cache implemented at level 5:b000 No cache.[11:9] Ctype4 Indicates the type of cache implemented at level 4:b000 No cache.[8:6] Ctype3 Indicates the type of cache implemented at level 3:b000 No cache.[5:3] Ctype2 Indicates the type of cache implemented at level 2:b100 Unified cache.[2:0] Ctype1 Indicates the type of cache implemented at level 1:b011 Separate instruction and data caches.To access the CLIDR, read the CP15 register with:MRC p15, 1, , c0, c0, 1 ; Read Cache Level ID Register4.3.23 Auxiliary ID RegisterThe processor does not implement AIDR, so this register is always RAZ/WI.4.3.24 Cache Size Selection RegisterThe CSSELR characteristics are:PurposeSelects the current CCSIDR, see Cache Size ID Register on page 4-48, byspecifying:• The required cache level.• The cache type, either instruction or data cache.Usage constraints The CSSELR is:• A read/write register.• Banked for the Secure and Non-secure states.• Only accessible from PL1 or higher.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-51ID062913Non-Confidential