ARM Cortex-A15 MPCore Processor Technical Reference Manual

Program Trace MacrocellIf the Programming bit is set, trace generation is stopped. The PTM then enters the idle state.This ensures that no trace packets remain. After the PTM completes the idle state transition withthe Programming bit set, reading the Status Register reports the Programming bit as set. TheProgramming bit must not be cleared until the Status Register reports the Programming bit asset.12.5.5 Interaction with the performance monitoring unitThe processor includes a Performance Monitoring Unit (PMU) that enables events, such ascache misses and instructions executed, to be counted over a period of time. This sectiondescribes how the PMU and PTM function together.Use of PMU events by the PTMAll PMU architectural events are available to the PTM through the extended input facility. Seethe ARM Architectural Reference Manual for more information on PMU events.The PTM uses two extended external input selectors to access the PMU events. Each selectorcan independently select one of the PMU events, which are then active for the cycles where therelevant events occur. These selected events can then be accessed by any of the event registerswithin the PTM.12.5.6 Effect of OS Double Lock on trace register accessAll trace register accesses through the memory-mapped and external debug interfaces behaveas if the processor power domain is off when OS Double Lock is set. For more information onOS Double Lock, see the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-Redition.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 12-10ID062913Non-Confidential