ARM Cortex-A15 MPCore Processor Technical Reference Manual

Memory Management Unit5.4 Memory access sequenceWhen the processor generates a memory access, the MMU:1. Performs a lookup for the requested virtual address, current ASID, current VMID, andsecurity state in the relevant L1 instruction or data load/store TLB.2. Performs a lookup for the requested virtual address, current ASID, current VMID, andsecurity state in the unified L2 TLB if there is a miss in the relevant L1 TLB.3. Performs a hardware translation table walk if there is a miss in the L2 TLB.You can configure the MMU to perform hardware translation table walks using either the classicVMSAv7 Short-descriptor translation table format, or the Long-descriptor translation tableformat specified by the LPAE. This is controlled by programming the Extended Address Enable(EAE) bit in the appropriate Secure or Non-secure Translation Table Base Control Register(TTBCR). See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition forinformation on translation table formats.NoteTranslations in Hyp mode and Stage2 translations are always performed with theLong-descriptor translation table format as specified by the LPAE.You can configure the MMU to perform translation table walks in cacheable regions using:• The Short-descriptor translation table format by setting the IRGN bits in the TranslationTable Base Register 0 (TTBR0) and Translation Table Base Register 1 (TTBR1).• The Long-descriptor translation table format by setting the IRGN bits in the relevantTranslation Table Base Control Register (TTBCR).If the encoding of the IRGN bits is Write-Back, an L1 data cache lookup is performed and datais read from the data cache. If the encoding of the IRGN bits is Write-Through orNon-Cacheable, an access to external memory is performed.In the case of an L2 TLB miss, the hardware does a translation table walk if the translation tablewalk is enabled by:• The Short-descriptor translation table format by clearing the PD0 or PD1 bit in theTTBCR.• The Long-descriptor translation table format by clearing the EPD0 or EPD1 bit in theTTBCR.If translation table walks are disabled, for example, PD0 or EPD0 is set to 1 for TTBR0, or PD1or EPD1 is set to 1 for TTBR1, the processor returns a Translation fault. If the TLB finds amatching entry, it uses the information in the entry as follows:• The access permission bits and the domain when using the Short-descriptor translationtable format, determine if the access is permitted. If the matching entry does not pass thepermission checks, the MMU signals a memory abort. See the ARM ® ArchitectureReference Manual ARMv7-A and ARMv7-R edition for a description of access permissionbits, abort types and priorities, and for a description of the Instruction Fault StatusRegister (IFSR) and Data Fault Status Register (DFSR).• The memory region attributes specified in the TLB entry determine if the access is:— Secure or Non-secure.— Inner, Outer shareable or not.— Normal Memory, Device, or Strongly-ordered.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 5-5ID062913Non-Confidential