ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlTable 4-61 DFSR bit assignments for Long-descriptor translation table format (continued)Bits Name Function[9] - RAO.[8:6] - Reserved, UNK/SBZP.[5:0] Status Fault Status bits. This field indicates the type of exception generated. Any encoding not listed isreserved:b0001LL Translation fault, LL bits indicate level.b0010LL Access flag fault, LL bits indicate level.b0011LL Permission fault, LL bits indicate level.b010000 Synchronous external abort.b011000 Synchronous parity error on memory access.b010001 Asynchronous external abort.b011001 Asynchronous parity error on memory access.b0101LL Synchronous external abort on translation table walk, LL bits indicate level.b0111LL Synchronous parity error on memory access on translation table walk, LL bitsindicate level.b100001 Alignment fault.b100010 Debug event.Table 4-62 shows how the LL bits in the Status field encode the lookup level associated with theMMU fault.Table 4-62 Encodings of LL bits associated with the MMU faultLL bitsMeaning00 Reserved01 First level10 Second level11 Third levelTo access the DFSR, read or write the CP15 register with:MRC p15, 0, , c5, c0, 0; Read Data Fault Status RegisterMCR p15, 0, , c5, c0, 0; Write Data Fault Status Register4.3.41 Instruction Fault Status RegisterThe IFSR characteristics are:PurposeHolds status information about the last instruction fault.Usage constraints The IFSR is:• A read/write register.• Banked for Secure and Non-secure states.• Accessible from PL1 or higher.ConfigurationsAvailable in all configurations.Attributes See the register summary in Table 4-6 on page 4-6.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-78ID062913Non-Confidential