ARM Cortex-A15 MPCore Processor Technical Reference Manual

NEON and VFP UnitTable 14-5 FPSCR bit assignments (continued)Bits Field Function[25] DN Default NaN mode control bit:0 NaN operands propagate through to the output of a floating-point operation.1 Any operation involving one or more NaNs returns the Default NaN.The value of this bit only controls VFP arithmetic. Advanced SIMD arithmetic always uses theDefault NaN setting, regardless of the value of the DN bit.[24] FZ Flush-to-zero mode control bit:0 Flush-to-zero mode disabled. Behavior of the floating-point system is fullycompliant with the IEEE 754 standard.1 Flush-to-zero mode enable.The value of this bit only controls VFP arithmetic. Advanced SIMD arithmetic always uses theFlush-to-zero setting, regardless of the value of the FZ bit.[23:22] RMode Rounding Mode control field:b00 Round to Nearest (RN) mode.b01 Round towards Plus Infinity (RP) mode.b10 Round towards Minus Infinity (RM) mode.b11 Round towards Zero (RZ) mode.The specified rounding mode is used by almost all VFP floating-point instructions. AdvancedSIMD arithmetic always uses the Round to Nearest setting, regardless of the value of the RModebits.[21:20] Stride Use of non-zero value in this field for VFP short vector operation is deprecated in ARMv7.If this field is set to a non-zero value, the VFP data processing operations, except Vector Compareand Vector Convert instructions, generate an Undefined Instruction exception.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition for moreinformation.[19] - UNK/SBZP.[18:16] Len Use of non-zero value in this field for VFP short vector operation is deprecated in ARMv7.If this field is set to a non-zero value, the VFP data processing operations, except Vector Compareand Vector Convert instructions, generate an Undefined Instruction exception.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R editionfor moreinformation.[15] - RAZ/SBZP.[14:13] - UNK/SBZP.[12:8] - RAZ/SBZP.[7] IDC Input Denormal cumulative exception bit.[6:5] - UNK/SBZP.[4] IXC Inexact cumulative exception bit.[3] UFC Underflow cumulative exception bit.[2] OFC Overflow cumulative exception bit.[1] DZC Division by Zero cumulative exception bit.[0] IOC Invalid Operation cumulative exception bit.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 14-9ID062913Non-Confidential