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ARM Cortex-A15 MPCore Processor Technical Reference Manual

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System ControlTable 4-59 HCPTR bit assignments (continued)Bits Name Function[11] TCP11 Trap coprocessor 11:0 If NSACR.CP11 is set to 1, then Hyp mode can access CP11, regardless of thevalue of CPACR.CP11.NoteThis bit value has no effect on possible use of CP11 from Non-secure PL1 and PL0modes.1 Trap valid Non-secure accesses to CP11 to Hyp mode.When TCP11 is set to 1, any otherwise-valid access to CP11 from:• A Non-secure PL1 or PL0 mode is trapped to Hyp mode.• Hyp mode generates an Undefined Instruction exception, taken in Hypmode.If VFP and NEON are not implemented, this bit is RAO/WI. See the <strong>ARM</strong> ® Architecture <strong>Reference</strong><strong>Manual</strong> <strong>ARM</strong>v7-A and <strong>ARM</strong>v7-R edition for more information.[10] TCP10 Trap coprocessor 10:0 If NSACR.CP10 is set to 1, then Hyp mode can access CP10, regardless of thevalue of CPACR.CP10.NoteThis bit value has no effect on possible use of CP10 from Non-secure PL1 and PL0modes.1 Trap valid Non-secure accesses to CP10 to Hyp mode.When TCP10 is set to 1, any otherwise-valid access to CP10 from:• A Non-secure PL1 or PL0 mode is trapped to Hyp mode.• Hyp mode generates an Undefined Instruction exception, taken in Hypmode.If VFP and NEON are not implemented, this bit is RAO/WI. See the <strong>ARM</strong> ® Architecture <strong>Reference</strong><strong>Manual</strong> <strong>ARM</strong>v7-A and <strong>ARM</strong>v7-R edition for more information.[9:0] - Reserved, RAO/WI.To access the HCPTR, read or write the CP15 register with:MRC p15, 4, , c1, c1, 2; Read Hyp Coprocessor Trap RegisterMCR p15, 4, , c1, c1, 2; Write Hyp Coprocessor Trap Register4.3.36 Hyp Auxiliary Configuration RegisterThe processor does not implement HACR, so this register is UNK/SBZP in Hyp mode and inMonitor mode when SCR.NS is 1.4.3.37 Translation Table Base Register 0 and Register 1The processor does not use any implementation-defined bits in the 32-bit TTBR0 and TTBR1format, so these bits are UNK/SBZP.4.3.38 Translation Table Base Control RegisterThe processor does not use any implementation-defined bits when using the Long-descriptortranslation table format, so these bits are UNK/SBZP.<strong>ARM</strong> DDI 0438I Copyright © 2011-2013 <strong>ARM</strong>. All rights reserved. 4-74ID062913Non-Confidential

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