ARM Cortex-A15 MPCore Processor Technical Reference Manual

System Control31 24 23 22 21 18 17 6 50RAMID = 0x10 Way Physical address [17:6]ReservedReservedThe RAMINDEX address bits for accessing L2 tag RAM are:Figure 4-53 RAMINDEX bit assignments for L2 tag RAMWay[3:0]PA[17:8]PA[7:6]Way select.Row select.Tag bank select.The data returned from accessing L2 tag RAM are:DL1DATA3 32'b0.DL1DATA2 32'b0.DL1DATA1 Tag ECC[6:0].DL1DATA0 Tag data[29:0].Figure 4-54 shows the RAMINDEX bit assignments for accessing L2 data RAM.31 24 23 22 21 18 17 4 3 0RAMID = 0x11 Way Physical address [17:4]ReservedReservedThe RAMINDEX address bits for accessing L2 data RAM are:Figure 4-54 RAMINDEX bit assignments for L2 data RAMWay[3:0]PA[17:8]PA[7:6]PA[5:4]Way select.Row select.Tag bank select.Data bank select.The data returned from accessing L2 data RAM are:DL1DATA3 Data[127:96].DL1DATA2 Data[95:64].DL1DATA1 Data[63:32].DL1DATA0 Data[31:0].Figure 4-55 on page 4-98 shows the RAMINDEX bit assignments for accessing L2 snoop tagRAM.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-97ID062913Non-Confidential