ARM Cortex-A15 MPCore Processor Technical Reference Manual

Functional DescriptionNoteFigure 2-15 shows that in the second denial sequence, QACTIVE is still deasserted when theretention request is denied. QACTIVE is an indication of processor activity, but is only a hint.A retention request can be accepted when QACTIVE is asserted HIGH, or denied whenQACTIVE is deasserted.CLKQACTIVEQREQnQACCEPTnQDENYSTANDBYWFIFigure 2-15 WFI denied retention timingEach processor present has an independent set of pins QREQn, QACCEPTn, QDENY, andQACTIVE. QREQn is a fully asynchronous input and can only transition from deassertedHIGH to asserted LOW if QACCEPTn is deasserted HIGH and QDENY is deasserted LOW.After QREQn is asserted LOW, it must be held asserted LOW until either QACCEPTn isasserted LOW or QDENY is asserted HIGH. QREQn can then be deasserted HIGH, and mustbe held deasserted HIGH until both QACCEPTn is deasserted HIGH and QDENY isdeasserted LOW.The QACTIVE pin is an activity hint that is not part of the strict 4-phase handshake of theQREQn, QACCEPTn, and QDENY pins. If QACTIVE is asserted HIGH while a processoris in quiescent state, it indicates that the external power controller can, but is not required to, exitquiescent state. If QACTIVE is asserted HIGH while the processor is not in quiescent state, itindicates that the processor is not in WFI standby or WFE low-power state and there is not alikely processor retention opportunity. If QACTIVE is deasserted, it indicates that the processoris in WFI or WFE low-power state and there might be an opportunity to put the processor intoquiescent state and lower its voltage.Performance impact on the use of processor retentionThe use of processor retention can impact performance. Any delay in deasserting QREQn whenQACTIVE is asserted HIGH during quiescent state can delay the starting of the clocks to thatprocessor. This directly impacts the performance of that processor if it exits WFI or WFElow-power state. This also impacts the performance of other processors or coherent memorymasters if that processor is being restarted to handle a cache snoop. In general, only use thisfeature if the system can enter and exit the retention voltage level in a very short period of time.Guidelines on the use of processor retentionAs processors generally only stay in WFE low-power state for a short period of time, ARMrecommends that you only take a processor into retention when it is in WFI low-power state.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 2-26ID062913Non-Confidential