ARM Cortex-A15 MPCore Processor Technical Reference Manual

DebugTable 10-15 shows the DBGPRCR bit assignments.Table 10-15 DBGPRCR bit assignmentsBits Name Function[31:4] - Reserved, UNK/SBZP.[3] COREPURQ Core Powerup Request bit. This bit enables a debugger to request that the power controller powersup the core, enabling access to the debug registers in the core power domain:0 DBGPWRUPREQ is LOW, this is the reset value.1 DBGPWRUPREQ is HIGH. This bit is only defined for the memory-mappedand external debug interfaces. For accesses to DBGPRCR from CP14, this bit isUNK/SBZP.This bit can be read and written when the core power domain is powered down, and whenDBGPRSR.DLK is set to 1. See the ARM ® Architecture Reference Manual ARMv7-A andARMv7-R edition for more information.[2] HCWR Hold Core Warm Reset bit. Writing 1 to this bit means the non-debug logic of the processor is heldin reset after a core is powered up or a warm reset:0 Does not hold the non-debug logic in reset on a power up or warm reset.1 Holds the non-debug logic of the processor in reset on a power up or a warm reset.The processor is held in this state until this bit is cleared to 0.For accesses to DBGPRCR from CP14, this bit is UNK/SBZP.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition for moreinformation.[1] CWRR Core Warm Reset Request bit. Writing 1 to this bit issues a request for a warm reset:0 No action.1 Request internal reset by asserting the DBGRSTREQ output HIGH for 16 or 64cycles. For more information, see bit[2] Debug extend core reset request of theDBGEACR, Debug External Auxiliary Control Register on page 10-13.Reads from this bit are UNKNOWN, and writes to this bit from the memory-mapped or externaldebug interface are ignored when any of the following apply:• The core power domain is powered down.• DBGPRSR.DLK, OS Double Lock status bit, is set to 1.• For the external debug interface, the OS lock is set.See the ARM ® Architecture Reference Manual ARMv7-A and ARMv7-R edition for moreinformation.[0] CORENPDRQ Core No Powerdown Request bit. When set to 1, the DBGNOPWRDWN output signal is HIGH.This output is connected to the system power controller and is interpreted as a request to operatein emulate mode. In this mode, the processor that includes PTM are not actually powered downwhen requested by software or hardware handshakes:0 DBGNOPWRDWN is LOW. This is the reset value.1 DBGNOPWRDWN is HIGH.This bit is UNKNOWN on reads and ignores writes when any of the following apply:• The core power domain is powered down. If the CORENPDRQ bit is 1, it loses this valuethrough the powerdown.• DBGPRSR.DLK, OS Double Lock status bit is set to 1.• For the external debug interface, the OS Lock is set.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 10-25ID062913Non-Confidential