ARM Cortex-A15 MPCore Processor Technical Reference Manual

System ControlBits Name Function31 29 28 27 26 25 2417 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0ReservedEnable replay thresholdsingle issue for currenttag bankEnable CPU WFI retentionmodeEnable UniqueCleanevictions with dataDisable SharedCleandata transfersDisable multiple outstandingWriteClean/WriteBack/Evictsusing the same AWIDDisable DSB with noDVM synchronizationDisable Non-secure debug array readDisable ACE DVM/CMO message broadcastEnable hazard-detect timeoutDisable ACE shareable transactionsfrom masterReservedDisable WriteUnique and WriteLineUniquetransactions from masterDisable clean/evict push to externalLimit to one request per tag bankEnable arbitration replay threshold timeoutDisable prefetch forwardingEnable replay threshold single issue for all tag banksEnable L2, GIC, and Timer regional clock gatesForce L2 logic clock enableForce L2 tag bank clock enableReservedTable 4-74 shows the L2ACTLR bit assignments.[31:29] - Reserved, RAZ/WI.ReservedFigure 4-59 L2ACTLR bit assignmentsTable 4-74 L2ACTLR bit assignments[28] Force L2 tag bank clockenable active[27] Force L2 logic clock enableactiveForces L2 tag bank clock enable active:0 Does not prevent the clock generator from stopping the L2 tag bankclock. This is the reset value.1 Prevents the clock generator from stopping the L2 tag bank clock.This bit applies to each of the four L2 cache tag bank clocks.Forces L2 logic clock enable active:0 Does not prevent the clock generator from stopping the L2 logic clock.This is the reset value.1 Prevents the clock generator from stopping the L2 logic clock.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. 4-101ID062913Non-Confidential