ARM Cortex-A15 MPCore Processor Technical Reference Manual

Signal DescriptionsA.5 Generic Interrupt Controller signalsSignal Type DescriptionTable A-4 shows the GIC signals. The value of N is one less than the number of processors inyour design.CFGSDISABLE a Input Disable write access to some secure GIC registers.Table A-4 GIC signalsIRQS[n:0] b Input Interrupt request input lines for the GIC where n can be 31, 63, up to 223 by increments of 32.nIRQ[N:0] Input Individual processor IRQ request input lines. Active-LOW, interrupt request:0 Activate interrupt.1 Do not activate interrupt.The processor treats the nIRQ input as level-sensitive. To guarantee that an interrupt is taken,the nIRQ input must be asserted until the processor acknowledges the interrupt.nFIQ[N:0] Input Individual processor FIQ request input line. Active-LOW, FIQ request:0 Activate FIQ request.1 Do not activate FIQ request.The processor treats the nFIQ input as level-sensitive. To guarantee that an interrupt is taken,the nFIQ input must be asserted until the processor acknowledges the interrupt.nVIRQ[N:0] Input Individual processor virtual IRQ request input lines. Active-LOW, interrupt request:0 Activate virtual IRQ request.1 Do not activate virtual IRQ request.The processor treats the nVIRQ input as level-sensitive. To guarantee that an interrupt is taken,the nVIRQ input must be asserted until the processor acknowledges the interrupt. If theCortex-A15 MPCore processor is configured to include the GIC, and the GIC is used, the inputpins nVIRQ and nVFIQ must be tied off to HIGH. If the processor is configured to include theGIC, and the GIC is not used, the input pins nVIRQ and nVFIQ can be driven by an externalGIC in the SoC.See GIC configuration on page 8-6 for more information.nVFIQ[N:0] Input Individual processor virtual FIQ request input lines. Active-LOW, virtual FIQ request:0 Activate virtual FIQ request.1 Do not activate virtual FIQ request.The processor treats the nVFIQ input as level-sensitive. To guarantee that an interrupt is taken,the nVFIQ input must be asserted until the processor acknowledges the interrupt. If theCortex-A15 MPCore processor is configured to include the GIC, and the GIC is used, the inputpins nVIRQ and nVFIQ must be tied off to HIGH. If the processor is configured to include theGIC, and the GIC is not used, the input pins nVIRQ and nVFIQ can be driven by an externalGIC in the SoC.See GIC configuration on page 8-6 for more information.nIRQOUT[N:0] a Output Active-LOW output of individual processor nIRQ from the GIC.For use when processors are powered down and interrupts from the GIC are routed to anexternal power controller.ARM DDI 0438I Copyright © 2011-2013 ARM. All rights reserved. A-6ID062913Non-Confidential